Try to leak counter values from secure world.
This patch introduces a series of tests that try to leak PMU counter values
from EL3 and S_EL1.
PMU events used:
- CPU cycles via PMU counter PMCCNTR_EL0
- Retired writes to PC via PMU counter PMEVCNTR0_EL0
This AARCH64-specific patch is for security fix:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/1789
The AARCH32 versions of these tests will be in a future patch.
Signed-off-by: Petre-Ionut Tudor <petre-ionut.tudor@arm.com>
Change-Id: Ib27948edadde30272e59a9ab208543703fa078bd
diff --git a/tftf/tests/tests-standard.xml b/tftf/tests/tests-standard.xml
index a1323d5..fa57621 100644
--- a/tftf/tests/tests-standard.xml
+++ b/tftf/tests/tests-standard.xml
@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="utf-8"?>
<!--
- Copyright (c) 2018, Arm Limited. All rights reserved.
+ Copyright (c) 2018-2019, Arm Limited. All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
-->
@@ -20,6 +20,7 @@
<!ENTITY tests-cpu-extensions SYSTEM "tests-cpu-extensions.xml">
<!ENTITY tests-performance SYSTEM "tests-performance.xml">
<!ENTITY tests-smc SYSTEM "tests-smc.xml">
+ <!ENTITY tests-pmu-leakage SYSTEM "tests-pmu-leakage.xml">
]>
<testsuites>
@@ -35,5 +36,6 @@
&tests-cpu-extensions;
&tests-performance;
&tests-smc;
+ &tests-pmu-leakage;
</testsuites>