feat(smccc): availability test: add FEAT_AIE and FEAT_PFAR checks
ARMv8.8 introduced FEAT_PFAR and FEAT_AIE, which each have a trap bit
in SCR_EL3.
Add the respective ID register fields and check for those two features
in the SMCCC feature availability test, to verify that EL3 has enabled
the right bits in the SCR_EL3 availability value.
Fix some whitespace damage in the MEC field definitions on the way.
Change-Id: I5a64f51ba6bcc04c271ddf1e7456ed584da6a1af
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index e408afa..72cd009 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -482,12 +482,22 @@
#define ID_AA64MMFR3_EL1_TCRX_WIDTH U(4)
#define ID_AA64MMFR3_EL1_TCR2_SUPPORTED ULL(0x1)
-#define ID_AA64MMFR3_EL1_MEC_SHIFT U(28)
-#define ID_AA64MMFR3_EL1_MEC_MASK ULL(0xf)
+#define ID_AA64MMFR3_EL1_AIE_SHIFT U(24)
+#define ID_AA64MMFR3_EL1_AIE_MASK ULL(0xf)
+#define ID_AA64MMFR3_EL1_AIE_WIDTH U(4)
+#define ID_AA64MMFR3_EL1_AIE_SUPPORTED ULL(0x1)
+
+#define ID_AA64MMFR3_EL1_MEC_SHIFT U(28)
+#define ID_AA64MMFR3_EL1_MEC_MASK ULL(0xf)
#define ID_AA64MMFR3_EL1_MEC_WIDTH U(4)
#define ID_AA64MMFR3_EL1_MEC_SUPPORTED ULL(0x1)
/* ID_AA64PFR1_EL1 definitions */
+#define ID_AA64PFR1_EL1_PFAR_SHIFT U(60)
+#define ID_AA64PFR1_EL1_PFAR_MASK ULL(0xf)
+#define ID_AA64PFR1_EL1_PFAR_WIDTH U(4)
+#define ID_AA64PFR1_EL1_PFAR_SUPPORTED ULL(1)
+
#define ID_AA64PFR1_EL1_DF2_SHIFT U(56)
#define ID_AA64PFR1_EL1_DF2_WIDTH U(4)
#define ID_AA64PFR1_EL1_DF2_MASK (0xf << ID_AA64PFR1_EL1_DF2_SHIFT)
diff --git a/include/lib/aarch64/arch_features.h b/include/lib/aarch64/arch_features.h
index dfc9850..d2b71ef 100644
--- a/include/lib/aarch64/arch_features.h
+++ b/include/lib/aarch64/arch_features.h
@@ -596,6 +596,18 @@
== ID_AA64MMFR3_EL1_MEC_SUPPORTED;
}
+static inline bool is_feat_aie_supported(void)
+{
+ return EXTRACT(ID_AA64MMFR3_EL1_AIE, read_id_aa64mmfr3_el1())
+ == ID_AA64MMFR3_EL1_AIE_SUPPORTED;
+}
+
+static inline bool is_feat_pfar_supported(void)
+{
+ return EXTRACT(ID_AA64PFR1_EL1_PFAR, read_id_aa64pfr1_el1())
+ == ID_AA64PFR1_EL1_PFAR_SUPPORTED;
+}
+
static inline bool is_feat_gic_supported(void)
{
return EXTRACT(ID_AA64PFR0_GIC, read_id_aa64pfr0_el1())
diff --git a/tftf/tests/runtime_services/arm_arch_svc/smccc_feature_availability.c b/tftf/tests/runtime_services/arm_arch_svc/smccc_feature_availability.c
index c897f87..f827522 100644
--- a/tftf/tests/runtime_services/arm_arch_svc/smccc_feature_availability.c
+++ b/tftf/tests/runtime_services/arm_arch_svc/smccc_feature_availability.c
@@ -93,6 +93,8 @@
CHECK_BIT_SET(is_feat_csv2_2_present, SCR_EnSCXT_BIT);
CHECK_BIT_SET(is_armv8_3_pauth_present, SCR_APK_BIT);
CHECK_BIT_SET(is_feat_ras_present, SCR_TERR_BIT);
+ CHECK_BIT_SET(is_feat_aie_supported, SCR_AIEn_BIT);
+ CHECK_BIT_SET(is_feat_pfar_supported, SCR_PFAREn_BIT);
CHECK_NO_BITS_SET(SCR_EL3);
reg = get_feature_for_reg(CPTR_EL3_OPCODE);