Explain why we set HCR.TGE bit
Change-Id: Id55a62e8610f0b162a26a0eeb8f69e4a87910ed7
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
diff --git a/tftf/framework/aarch32/arch.c b/tftf/framework/aarch32/arch.c
index 763ea1a..2d023cd 100644
--- a/tftf/framework/aarch32/arch.c
+++ b/tftf/framework/aarch32/arch.c
@@ -14,5 +14,10 @@
if (!IS_IN_HYP())
panic();
+ /*
+ * Route physical interrupts to Hyp mode regardless of the value of the
+ * IMO/FMO bits. Without this, interrupts would not be taken and would
+ * remain pending, regardless of the PSTATE.{A, I, F} interrupt masks.
+ */
write_hcr(HCR_TGE_BIT);
}
diff --git a/tftf/framework/aarch64/arch.c b/tftf/framework/aarch64/arch.c
index dfaa9d1..0cdfd65 100644
--- a/tftf/framework/aarch64/arch.c
+++ b/tftf/framework/aarch64/arch.c
@@ -10,6 +10,12 @@
{
/* Do not try to configure EL2 if TFTF is running at NS-EL1 */
if (IS_IN_EL2()) {
+ /*
+ * Route physical interrupts to EL2 regardless of the value of
+ * the IMO/FMO bits. Without this, interrupts would not be taken
+ * and would remain pending, regardless of the PSTATE.{A, I, F}
+ * interrupt masks.
+ */
write_hcr_el2(HCR_TGE_BIT);
isb();
}