commit d1a7f4d2bd6b4867a71366b58b00759724ef99d1
author Igor Podgainõi <igor.podgainoi@arm.com> Tue Nov 26 12:50:47 2024 +0100
committer Manish Pandey <manish.pandey2@arm.com> Thu Dec 19 14:51:47 2024 +0000
tree 7439900358c0026fe7c781e725e6ba0b1c3fd37b
parent 5d10ae70d57bc836d417b7a7592ecc96a528bc38

feat: add tests to check SCTLR2, THE and D128 sysregs

This patch adds test cases for verifying that the system registers of
FEAT_SCTLR2, FEAT_THE and FEAT_D128 (FEAT_SYSREG128) are working
correctly by performing a series of reads and writes to the registers.

Change-Id: I5c102daa358a7ec5d1801395bc875e9850e83939
Signed-off-by: Igor Podgainõi <igor.podgainoi@arm.com>
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>

lib/extensions/sysreg128/aarch64/sysreg128_helpers.S

diff --git a/lib/extensions/sysreg128/aarch64/sysreg128_helpers.S b/lib/extensions/sysreg128/aarch64/sysreg128_helpers.S
new file mode 100644
index 0000000..27db8b1
--- /dev/null
+++ b/lib/extensions/sysreg128/aarch64/sysreg128_helpers.S
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <asm_macros.S>
+
+#if __aarch64__
+
+    .globl read128_par_el1
+    .globl read128_ttbr0_el1
+    .globl read128_ttbr1_el1
+    .globl read128_ttbr0_el2
+    .globl read128_ttbr1_el2
+    .globl read128_vttbr_el2
+    .globl read128_rcwmask_el1
+    .globl read128_rcwsmask_el1
+    .globl write128_par_el1
+    .globl write128_ttbr0_el1
+    .globl write128_ttbr1_el1
+    .globl write128_ttbr0_el2
+    .globl write128_ttbr1_el2
+    .globl write128_vttbr_el2
+    .globl write128_rcwmask_el1
+    .globl write128_rcwsmask_el1
+
+func read128_par_el1 /* MRRS x0, x1, S3_0_C7_C4_0 */
+    .inst 0xD5787400
+    ret
+endfunc read128_par_el1
+
+func read128_ttbr0_el1 /* MRRS x0, x1, S3_0_C2_C0_0 */
+    .inst 0xD5782000
+    ret
+endfunc read128_ttbr0_el1
+
+func read128_ttbr1_el1 /* MRRS x0, x1, S3_0_C2_C0_1 */
+    .inst 0xD5782020
+    ret
+endfunc read128_ttbr1_el1
+
+func read128_ttbr0_el2 /* MRRS x0, x1, S3_4_C2_C0_0 */
+    .inst 0xD57C2000
+    ret
+endfunc read128_ttbr0_el2
+
+func read128_ttbr1_el2 /* MRRS x0, x1, S3_4_C2_C0_1 */
+    .inst 0xD57C2020
+    ret
+endfunc read128_ttbr1_el2
+
+func read128_vttbr_el2 /* MRRS x0, x1, S3_4_C2_C1_0 */
+    .inst 0xD57C2100
+    ret
+endfunc read128_vttbr_el2
+
+func read128_rcwmask_el1 /* MRRS x0, x1, S3_0_C13_C0_6 */
+    .inst 0xD578D0C0
+    ret
+endfunc read128_rcwmask_el1
+
+func read128_rcwsmask_el1 /* MRRS x0, x1, S3_0_C13_C0_3 */
+    .inst 0xD578D060
+    ret
+endfunc read128_rcwsmask_el1
+
+func write128_par_el1 /* MSRR S3_0_C7_C4_0, x0, x1 */
+    .inst 0xD5587400
+    ret
+endfunc write128_par_el1
+
+func write128_ttbr0_el1 /* MSRR S3_0_C2_C0_0, x0, x1 */
+    .inst 0xD5582000
+    ret
+endfunc write128_ttbr0_el1
+
+func write128_ttbr1_el1 /* MSRR S3_0_C2_C0_1, x0, x1 */
+    .inst 0xD5582020
+    ret
+endfunc write128_ttbr1_el1
+
+func write128_ttbr0_el2 /* MSRR S3_4_C2_C0_0, x0, x1 */
+    .inst 0xD55C2000
+    ret
+endfunc write128_ttbr0_el2
+
+func write128_ttbr1_el2 /* MSRR S3_4_C2_C0_1, x0, x1 */
+    .inst 0xD55C2020
+    ret
+endfunc write128_ttbr1_el2
+
+func write128_vttbr_el2 /* MSRR S3_4_C2_C1_0, x0, x1 */
+    .inst 0xD55C2100
+    ret
+endfunc write128_vttbr_el2
+
+func write128_rcwmask_el1 /* MSRR S3_0_C13_C0_6, x0, x1 */
+    .inst 0xD558D0C0
+    ret
+endfunc write128_rcwmask_el1
+
+func write128_rcwsmask_el1 /* MSRR S3_0_C13_C0_3, x0, x1 */
+    .inst 0xD558D060
+    ret
+endfunc write128_rcwsmask_el1
+
+#endif /* __aarch64__ */