refactor(sgi): regroup "sgi" and "rdinfra" to "neoverse_rd"
Currently, reference design platforms such as RD-N2, RD-N1-Edge, RD-V1,
and SGI-575 utilize "sgi/common" as the common source directory. The
"sgi" prefix originated from the System Guidance Infrastructure (SGI)
and was initially associated with the SGI-575 platform. However,
subsequent platforms released were under the Neoverse reference design
product name.
To align with the Neoverse reference design nomenclature, regroup all
common and board files within neoverse_rd directory. Consolidate common
sources and headers under neoverse_rd/common. Board files for RD-V1,
RD-N2, RD-N1-Edge and SGI-575 are moved to neoverse_rd/platform. With
the changes in this commit, the tree view would look as follows:
├── neoverse_rd
│ ├── common
│ │ ├── arch
│ │ └── include
│ └── platform
│ ├── rdn1edge
│ ├── rdn2
│ ├── rdv1
│ └── sgi575
Additionally, update all file prefixes from "sgi" to "nrd."
Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: I07e2af143fad82e48172612fe0e28db6464fa901
diff --git a/plat/arm/neoverse_rd/common/arch/aarch64/plat_helpers.S b/plat/arm/neoverse_rd/common/arch/aarch64/plat_helpers.S
new file mode 100644
index 0000000..647bdaf
--- /dev/null
+++ b/plat/arm/neoverse_rd/common/arch/aarch64/plat_helpers.S
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <asm_macros.S>
+#include <drivers/arm/pl011.h>
+#include <platform_def.h>
+
+ .globl platform_get_core_pos
+ .globl plat_crash_console_init
+ .globl plat_crash_console_putc
+ .globl plat_crash_console_flush
+
+/*----------------------------------------------------------------------
+ * unsigned int platform_get_core_pos(unsigned long mpid)
+ *
+ * Function to calculate the core position on sgi platforms.
+ *
+ * (ClusterId * CSS_SGI_MAX_CPUS_PER_CLUSTER * CSS_SGI_MAX_PE_PER_CPU) +
+ * (CPUId * CSS_SGI_MAX_PE_PER_CPU) +
+ * ThreadId
+ *
+ * which can be simplified as:
+ *
+ * ((ClusterId * CSS_SGI_MAX_CPUS_PER_CLUSTER + CPUId) * CSS_SGI_MAX_PE_PER_CPU)
+ * + ThreadId
+ * ---------------------------------------------------------------------
+ */
+func platform_get_core_pos
+ /*
+ * Check for MT bit in MPIDR. If not set, shift MPIDR to left to make it
+ * look as if in a multi-threaded implementation.
+ */
+ tst x0, #MPIDR_MT_MASK
+ lsl x3, x0, #MPIDR_AFFINITY_BITS
+ csel x3, x3, x0, eq
+
+ /* Extract individual affinity fields from MPIDR */
+ ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
+ ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
+ ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
+
+ /* Compute linear position */
+ mov x3, #CSS_SGI_MAX_CPUS_PER_CLUSTER
+ madd x1, x2, x3, x1
+ mov x3, #CSS_SGI_MAX_PE_PER_CPU
+ madd x0, x1, x3, x0
+ ret
+endfunc platform_get_core_pos
+
+/* ---------------------------------------------
+ * int plat_crash_console_init(void)
+ * Function to initialize the crash console
+ * without a C Runtime to print crash report.
+ * Clobber list : x0 - x4
+ * ---------------------------------------------
+ */
+func plat_crash_console_init
+ mov_imm x0, PLAT_ARM_UART_BASE
+ mov_imm x1, PLAT_ARM_UART_CLK_IN_HZ
+ mov_imm x2, PL011_BAUDRATE
+ b console_core_init
+endfunc plat_crash_console_init
+
+/* ---------------------------------------------
+ * int plat_crash_console_putc(int c)
+ * Function to print a character on the crash
+ * console without a C Runtime.
+ * Clobber list : x1, x2
+ * ---------------------------------------------
+ */
+func plat_crash_console_putc
+ mov_imm x1, PLAT_ARM_UART_BASE
+ b console_core_putc
+endfunc plat_crash_console_putc
+
+/* ---------------------------------------------
+ * int plat_crash_console_flush()
+ * Function to force a write of all buffered
+ * data that hasn't been output.
+ * Out : return -1 on error else return 0.
+ * Clobber list : r0 - r1
+ * ---------------------------------------------
+ */
+func plat_crash_console_flush
+ mov_imm x1, PLAT_ARM_UART_BASE
+ b console_core_flush
+endfunc plat_crash_console_flush
diff --git a/plat/arm/neoverse_rd/common/include/nrd_base_platform_def.h b/plat/arm/neoverse_rd/common/include/nrd_base_platform_def.h
new file mode 100644
index 0000000..672eb80
--- /dev/null
+++ b/plat/arm/neoverse_rd/common/include/nrd_base_platform_def.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef NRD_BASE_PLATFORM_DEF_H
+#define NRD_BASE_PLATFORM_DEF_H
+
+#include <lib/utils_def.h>
+
+/* Platform binary types for linking */
+#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
+#define PLATFORM_LINKER_ARCH aarch64
+
+/* Sub-system Peripherals */
+#define SGI_DEVICE0_BASE UL(0x2A000000)
+#define SGI_DEVICE0_SIZE UL(0x26000000)
+
+/* Peripherals and PCIe expansion area */
+#define SGI_DEVICE1_BASE UL(0x60000000)
+#define SGI_DEVICE1_SIZE UL(0x20000000)
+
+/* AP Non-Secure UART related constants */
+#define SGI_CSS_NSEC_UART_BASE UL(0x2A400000)
+#define SGI_CSS_NSEC_CLK_IN_HZ 7372800
+
+#define PLAT_ARM_UART_BASE SGI_CSS_NSEC_UART_BASE
+#define PLAT_ARM_UART_CLK_IN_HZ SGI_CSS_NSEC_CLK_IN_HZ
+
+/* Base address of trusted watchdog (SP805) */
+#define SP805_TWDOG_BASE UL(0x2A480000)
+
+/* Memory mapped Generic timer interfaces */
+#define SYS_CNT_BASE1 UL(0x2A830000)
+
+/* DRAM base address and size */
+#define PLAT_ARM_DRAM1_BASE UL(0x80000000)
+#define PLAT_ARM_DRAM1_SIZE UL(0x80000000)
+#define DRAM_BASE PLAT_ARM_DRAM1_BASE
+
+/* TF-A reserves DRAM space 0xFF000000- 0xFFFFFFFF for TZC */
+#define DRAM_SIZE (PLAT_ARM_DRAM1_SIZE - 0x1000000)
+
+/* Base address and size of external NVM flash */
+#define FLASH_BASE UL(0x08000000)
+#define FLASH_SIZE UL(0x04000000) /* 64MB */
+#define NOR_FLASH_BLOCK_SIZE UL(0x40000) /* 256KB */
+
+/*******************************************************************************
+ * Run-time address of the TFTF image.
+ * It has to match the location where the Trusted Firmware-A loads the BL33
+ * image.
+ ******************************************************************************/
+#define TFTF_BASE UL(0xE0000000)
+
+/*
+ * If you want to use DRAM for non-volatile memory then the first 128MB
+ * can be used. However for tests that involve power resets this is not
+ * suitable since the state will be lost.
+ */
+#define TFTF_NVM_OFFSET 0x0
+#define TFTF_NVM_SIZE UL(0x08000000) /* 128 MB */
+
+/* Size of cacheable stacks */
+#define PLATFORM_STACK_SIZE 0x1400
+
+/* Size of coherent stacks */
+#define PCPU_DV_MEM_STACK_SIZE 0x600
+
+#define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \
+ CSS_SGI_MAX_CPUS_PER_CLUSTER)
+#define PLATFORM_NUM_AFFS (PLAT_ARM_CLUSTER_COUNT + PLATFORM_CORE_COUNT)
+#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL1
+
+#define PLAT_MAX_PWR_LEVEL PLATFORM_MAX_AFFLVL
+#define PLAT_MAX_PWR_STATES_PER_LVL 2
+
+/* Local state bit width for each level in the state-ID field of power state */
+#define PLAT_LOCAL_PSTATE_WIDTH 4
+
+/* Platform specific page table and MMU setup constants */
+#define MAX_XLAT_TABLES 6
+#define MAX_MMAP_REGIONS 16
+
+/*******************************************************************************
+ * Used to align variables on the biggest cache line size in the platform.
+ * This is known only to the platform as it might have a combination of
+ * integrated and external caches.
+ ******************************************************************************/
+#define CACHE_WRITEBACK_SHIFT 6
+#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
+
+/* Times(in ms) used by test code for completion of different events */
+#define PLAT_SUSPEND_ENTRY_TIME 15
+#define PLAT_SUSPEND_ENTRY_EXIT_TIME 30
+
+/* I/O Storage NOR flash device */
+#define MAX_IO_DEVICES 1
+#define MAX_IO_HANDLES 1
+
+/* Non-Secure Software Generated Interupts IDs */
+#define IRQ_NS_SGI_0 0
+#define IRQ_NS_SGI_7 7
+
+/* Per-CPU Hypervisor Timer Interrupt ID */
+#define IRQ_PCPU_HP_TIMER 26
+
+#endif /* NRD_BASE_PLATFORM_DEF_H */
diff --git a/plat/arm/neoverse_rd/common/include/nrd_soc_css_def.h b/plat/arm/neoverse_rd/common/include/nrd_soc_css_def.h
new file mode 100644
index 0000000..bffe189
--- /dev/null
+++ b/plat/arm/neoverse_rd/common/include/nrd_soc_css_def.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef NRD_SOC_CSS_DEF_H
+#define NRD_SOC_CSS_DEF_H
+
+/* Trusted watchdog (SP805) Interrupt ID */
+#define IRQ_TWDOG_INTID 86
+
+/* Maximum SPI */
+#define PLAT_MAX_SPI_OFFSET_ID 64
+
+/* AP_REFCLK Generic Timer, Non-secure. */
+#define IRQ_CNTPSIRQ1 92
+
+#endif /* NRD_SOC_CSS_DEF_H */
diff --git a/plat/arm/neoverse_rd/common/include/nrd_soc_css_def_v2.h b/plat/arm/neoverse_rd/common/include/nrd_soc_css_def_v2.h
new file mode 100644
index 0000000..5d4f5e6
--- /dev/null
+++ b/plat/arm/neoverse_rd/common/include/nrd_soc_css_def_v2.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef NRD_SOC_CSS_DEF_V2_H
+#define NRD_SOC_CSS_DEF_V2_H
+
+/* Trusted watchdog (SP805) Interrupt ID */
+#define IRQ_TWDOG_INTID 107
+
+/* Maximum SPI */
+#define PLAT_MAX_SPI_OFFSET_ID 256
+
+/* AP_REFCLK Generic Timer, Non-secure. */
+#define IRQ_CNTPSIRQ1 109
+
+#endif /* NRD_SOC_CSS_DEF_V2_H */
+
diff --git a/plat/arm/neoverse_rd/common/include/nrd_soc_platform_def.h b/plat/arm/neoverse_rd/common/include/nrd_soc_platform_def.h
new file mode 100644
index 0000000..d329688
--- /dev/null
+++ b/plat/arm/neoverse_rd/common/include/nrd_soc_platform_def.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2022-2024, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef NRD_SOC_PLATFORM_H
+#define NRD_SOC_PLATFORM_H
+
+#include <nrd_base_platform_def.h>
+#include <nrd_soc_css_def.h>
+
+/* Base address of non-trusted watchdog (SP805) */
+#define SP805_WDOG_BASE UL(0x1C0F0000)
+
+#endif /* NRD_SOC_PLATFORM_H */
diff --git a/plat/arm/neoverse_rd/common/include/nrd_soc_platform_def_v2.h b/plat/arm/neoverse_rd/common/include/nrd_soc_platform_def_v2.h
new file mode 100644
index 0000000..7a23c51
--- /dev/null
+++ b/plat/arm/neoverse_rd/common/include/nrd_soc_platform_def_v2.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2022-2024, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef NRD_SOC_PLATFORM_V2_H
+#define NRD_SOC_PLATFORM_V2_H
+
+#include <nrd_base_platform_def.h>
+#include <nrd_soc_css_def_v2.h>
+
+/* Base address of non-trusted watchdog (SP805) */
+#define SP805_WDOG_BASE UL(0x0C0F0000)
+
+#endif /* NRD_SOC_PLATFORM_V2_H */
diff --git a/plat/arm/neoverse_rd/common/nrd_common.mk b/plat/arm/neoverse_rd/common/nrd_common.mk
new file mode 100644
index 0000000..14195db
--- /dev/null
+++ b/plat/arm/neoverse_rd/common/nrd_common.mk
@@ -0,0 +1,27 @@
+#
+# Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+PLAT_INCLUDES := -Iplat/arm/neoverse_rd/common/include/
+
+PLAT_SOURCES := drivers/arm/gic/arm_gic_v2v3.c \
+ drivers/arm/gic/gic_v2.c \
+ drivers/arm/gic/gic_v3.c \
+ drivers/arm/sp805/sp805.c \
+ drivers/arm/timer/private_timer.c \
+ drivers/arm/timer/system_timer.c \
+ plat/arm/neoverse_rd/common/arch/${ARCH}/plat_helpers.S\
+ plat/arm/neoverse_rd/common/plat_setup.c \
+ plat/arm/neoverse_rd/common/nrd_mem_prot.c \
+ plat/arm/neoverse_rd/common/nrd_pwr_state.c
+
+include plat/arm/common/arm_common.mk
+
+ifeq (${USE_NVM},1)
+$(error "USE_NVM is not supported on SGI platforms")
+endif
+
+# Pass CSS_SGI_PLATFORM_VARIANT flag to the build system
+$(eval $(call add_define,TFTF_DEFINES,CSS_SGI_PLATFORM_VARIANT))
diff --git a/plat/arm/neoverse_rd/common/nrd_mem_prot.c b/plat/arm/neoverse_rd/common/nrd_mem_prot.c
new file mode 100644
index 0000000..09504e0
--- /dev/null
+++ b/plat/arm/neoverse_rd/common/nrd_mem_prot.c
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <platform.h>
+
+#define SGI_DRAM1_NS_START (TFTF_BASE + 0x4000000)
+#define SGI_DRAM1_NS_SIZE 0x10000000
+
+static const mem_region_t sgi_ram_ranges[] = {
+ { SGI_DRAM1_NS_START, SGI_DRAM1_NS_SIZE },
+};
+
+const mem_region_t *plat_get_prot_regions(int *nelem)
+{
+ *nelem = ARRAY_SIZE(sgi_ram_ranges);
+ return sgi_ram_ranges;
+}
diff --git a/plat/arm/neoverse_rd/common/nrd_pwr_state.c b/plat/arm/neoverse_rd/common/nrd_pwr_state.c
new file mode 100644
index 0000000..7b01257
--- /dev/null
+++ b/plat/arm/neoverse_rd/common/nrd_pwr_state.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <platform.h>
+#include <psci.h>
+
+/* State IDs for local power states on SGI platforms. */
+#define SGI_PS_RUN_STATE_ID 0 /* Valid for CPUs and Clusters */
+#define SGI_PS_RETENTION_STATE_ID 1 /* Valid for only CPUs */
+#define SGI_PS_OFF_STATE_ID 2 /* Valid for CPUs and Clusters */
+
+/* Suspend depth definitions for each power state */
+#define SGI_PS_RUN_DEPTH 0
+#define SGI_PS_RETENTION_DEPTH 1
+#define SGI_PS_OFF_DEPTH 2
+
+/* The state property array with details of idle state possible for the core */
+static const plat_state_prop_t core_state_prop[] = {
+ {SGI_PS_RETENTION_DEPTH, SGI_PS_RETENTION_STATE_ID,
+ PSTATE_TYPE_STANDBY},
+ {SGI_PS_OFF_DEPTH, SGI_PS_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN},
+ {0},
+};
+
+/* The state property array with details of idle state possible for the cluster */
+static const plat_state_prop_t cluster_state_prop[] = {
+ {SGI_PS_OFF_DEPTH, SGI_PS_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN},
+ {0},
+};
+
+const plat_state_prop_t *plat_get_state_prop(unsigned int level)
+{
+ switch (level) {
+ case MPIDR_AFFLVL0:
+ return core_state_prop;
+ case MPIDR_AFFLVL1:
+ return cluster_state_prop;
+ default:
+ return NULL;
+ }
+}
diff --git a/plat/arm/neoverse_rd/common/plat_setup.c b/plat/arm/neoverse_rd/common/plat_setup.c
new file mode 100644
index 0000000..e6d4c0d
--- /dev/null
+++ b/plat/arm/neoverse_rd/common/plat_setup.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <drivers/arm/arm_gic.h>
+#include <xlat_tables_v2.h>
+
+static const mmap_region_t mmap[] = {
+ MAP_REGION_FLAT(SGI_DEVICE0_BASE, SGI_DEVICE0_SIZE,
+ MT_DEVICE | MT_RW | MT_NS),
+ MAP_REGION_FLAT(SGI_DEVICE1_BASE, SGI_DEVICE1_SIZE,
+ MT_DEVICE | MT_RW | MT_NS),
+ MAP_REGION_FLAT(DRAM_BASE, TFTF_BASE - DRAM_BASE,
+ MT_MEMORY | MT_RW | MT_NS),
+ {0}
+};
+
+const mmap_region_t *tftf_platform_get_mmap(void)
+{
+ return mmap;
+}
+
+void plat_arm_gic_init(void)
+{
+ arm_gic_init(PLAT_ARM_GICC_BASE, PLAT_ARM_GICD_BASE, PLAT_ARM_GICR_BASE);
+}