feat(amu): test AMU counter restriction (RAZ)
When using AMU counters, there is risk of exposing information to
lower exception levels. In order to prevent this, counters are
restricted, so they are read as zero (RAZ) at a lower EL. This
test verifies that counters are read as zero after forcing counting
through instructions that trigger MPMM "gear shifting" (e.g.: by
executing SVE instructions).
Note: This test applies to TC2 only, as it is the only platform that
supports MPMM currently.
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: Ic32ba19fa489cf479947d4467ddb84e6abd1b454
diff --git a/tftf/tests/tests-cpu-extensions.xml b/tftf/tests/tests-cpu-extensions.xml
index 3b93344..bd6abdd 100644
--- a/tftf/tests/tests-cpu-extensions.xml
+++ b/tftf/tests/tests-cpu-extensions.xml
@@ -11,6 +11,7 @@
<testsuite name="CPU extensions" description="Various CPU extensions tests">
<testcase name="AMUv1 valid counter values" function="test_amu_valid_ctr" />
<testcase name="AMUv1 suspend/resume" function="test_amu_suspend_resume" />
+ <testcase name="AMUv1 group 1 RAZ" function="test_amu_group1_raz" />
<testcase name="SVE support" function="test_sve_support" />
<testcase name="Access Pointer Authentication Registers" function="test_pauth_reg_access" />
<testcase name="Use Pointer Authentication Instructions" function="test_pauth_instructions" />