feat(amu): test AMU counter restriction (RAZ)
When using AMU counters, there is risk of exposing information to
lower exception levels. In order to prevent this, counters are
restricted, so they are read as zero (RAZ) at a lower EL. This
test verifies that counters are read as zero after forcing counting
through instructions that trigger MPMM "gear shifting" (e.g.: by
executing SVE instructions).
Note: This test applies to TC2 only, as it is the only platform that
supports MPMM currently.
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: Ic32ba19fa489cf479947d4467ddb84e6abd1b454
diff --git a/include/lib/extensions/amu_private.h b/include/lib/extensions/amu_private.h
index 7ae17d9..b98178f 100644
--- a/include/lib/extensions/amu_private.h
+++ b/include/lib/extensions/amu_private.h
@@ -11,6 +11,10 @@
uint64_t amu_group0_cnt_read_internal(unsigned int idx);
uint64_t amu_group1_cnt_read_internal(unsigned int idx);
+uint64_t amu_group1_num_counters_internal(void);
+uint64_t amu_group1_is_cnt_impl_internal(unsigned int idx);
+void amu_group1_evtype_write_internal(unsigned int idx, uint64_t val);
+uint64_t amu_group1_evtype_read_internal(unsigned int idx);
#if __aarch64__
uint64_t amu_group0_voffset_read_internal(unsigned int idx);