feat(amu): test AMU counter restriction (RAZ)
When using AMU counters, there is risk of exposing information to
lower exception levels. In order to prevent this, counters are
restricted, so they are read as zero (RAZ) at a lower EL. This
test verifies that counters are read as zero after forcing counting
through instructions that trigger MPMM "gear shifting" (e.g.: by
executing SVE instructions).
Note: This test applies to TC2 only, as it is the only platform that
supports MPMM currently.
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: Ic32ba19fa489cf479947d4467ddb84e6abd1b454
diff --git a/include/lib/extensions/amu.h b/include/lib/extensions/amu.h
index d5950ca..3ce053d 100644
--- a/include/lib/extensions/amu.h
+++ b/include/lib/extensions/amu.h
@@ -71,7 +71,11 @@
#if AMU_GROUP1_NR_COUNTERS
uint64_t amu_group1_cnt_read(unsigned int idx);
+uint64_t amu_group1_num_counters(void);
+uint64_t amu_group1_evtype_read(unsigned int idx);
+void amu_group1_evtype_write(unsigned int idx, uint64_t val);
#if __aarch64__
+uint64_t amu_group1_is_counter_implemented(unsigned int idx);
uint64_t amu_group1_voffset_read(unsigned int idx);
void amu_group1_voffset_write(unsigned int idx, uint64_t val);
#endif