refactor(tc): Make tc0 tftf code generic to tc.
This code can be used for tc0, tc1 and tc2 testing so change from
tc0 naming to tc.
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Change-Id: Ied011db0cd688936d6ba20e48c5206de4891e732
diff --git a/plat/arm/tc0/aarch64/plat_helpers.S b/plat/arm/tc/aarch64/plat_helpers.S
similarity index 88%
rename from plat/arm/tc0/aarch64/plat_helpers.S
rename to plat/arm/tc/aarch64/plat_helpers.S
index 863b378..17c3c5f 100644
--- a/plat/arm/tc0/aarch64/plat_helpers.S
+++ b/plat/arm/tc/aarch64/plat_helpers.S
@@ -16,15 +16,15 @@
/*----------------------------------------------------------------------
* unsigned int platform_get_core_pos(unsigned long mpid)
*
- * Function to calculate the core position on TC0 platforms.
+ * Function to calculate the core position on TC platforms.
*
- * (ClusterId * TC0_MAX_CPUS_PER_CLUSTER * TC0_MAX_PE_PER_CPU) +
- * (CPUId * TC0_MAX_PE_PER_CPU) +
+ * (ClusterId * TC_MAX_CPUS_PER_CLUSTER * TC_MAX_PE_PER_CPU) +
+ * (CPUId * TC_MAX_PE_PER_CPU) +
* ThreadId
*
* which can be simplified as:
*
- * ((ClusterId * TC0_MAX_CPUS_PER_CLUSTER + CPUId) * TC0_MAX_PE_PER_CPU)
+ * ((ClusterId * TC_MAX_CPUS_PER_CLUSTER + CPUId) * TC_MAX_PE_PER_CPU)
* + ThreadId
* ---------------------------------------------------------------------
*/
@@ -43,9 +43,9 @@
ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
/* Compute linear position */
- mov x3, #TC0_MAX_CPUS_PER_CLUSTER
+ mov x3, #TC_MAX_CPUS_PER_CLUSTER
madd x1, x2, x3, x1
- mov x3, #TC0_MAX_PE_PER_CPU
+ mov x3, #TC_MAX_PE_PER_CPU
madd x0, x1, x3, x0
ret
endfunc platform_get_core_pos
diff --git a/plat/arm/tc0/include/platform_def.h b/plat/arm/tc/include/platform_def.h
similarity index 86%
rename from plat/arm/tc0/include/platform_def.h
rename to plat/arm/tc/include/platform_def.h
index 2fa17e6..1f0c28d 100644
--- a/plat/arm/tc0/include/platform_def.h
+++ b/plat/arm/tc/include/platform_def.h
@@ -12,9 +12,9 @@
#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
#define PLATFORM_LINKER_ARCH aarch64
-#define TC0_CLUSTER_COUNT 1
-#define TC0_MAX_CPUS_PER_CLUSTER 8
-#define TC0_MAX_PE_PER_CPU 1
+#define TC_CLUSTER_COUNT 1
+#define TC_MAX_CPUS_PER_CLUSTER 8
+#define TC_MAX_PE_PER_CPU 1
/*******************************************************************************
* Run-time address of the TFTF image.
@@ -23,9 +23,9 @@
******************************************************************************/
#define TFTF_BASE 0xE0000000
-#define TC0_DRAM1_BASE 0x80000000
-#define TC0_DRAM1_SIZE 0x80000000
-#define DRAM_BASE TC0_DRAM1_BASE
+#define TC_DRAM1_BASE 0x80000000
+#define TC_DRAM1_SIZE 0x80000000
+#define DRAM_BASE TC_DRAM1_BASE
/*
* TF-A reserves DRAM space 0xFD000000 - 0xFEFFFFFF for Trusted DRAM
@@ -34,7 +34,7 @@
#define ARM_TZC_DRAM1_SIZE 0x01000000
#define ARM_TRUSTED_DRAM1_SIZE 0x02000000
-#define DRAM_SIZE (TC0_DRAM1_SIZE - \
+#define DRAM_SIZE (TC_DRAM1_SIZE - \
ARM_TRUSTED_DRAM1_SIZE - \
ARM_TZC_DRAM1_SIZE)
@@ -67,17 +67,17 @@
#define TFTF_NVM_SIZE 0x8000000 /* 128 MB */
/* Sub-system Peripherals */
-#define TC0_DEVICE0_BASE 0x21000000
-#define TC0_DEVICE0_SIZE 0x5f000000
+#define TC_DEVICE0_BASE 0x21000000
+#define TC_DEVICE0_SIZE 0x5f000000
/* Following covers Peripherals and PCIe expansion area */
-#define TC0_DEVICE1_BASE 0x60000000
-#define TC0_DEVICE1_SIZE 0x20000000
+#define TC_DEVICE1_BASE 0x60000000
+#define TC_DEVICE1_SIZE 0x20000000
/* GIC-600 & interrupt handling related constants */
-#define TC0_GICD_BASE 0x30000000
-#define TC0_GICR_BASE 0x30080000
-#define TC0_GICC_BASE 0x2C000000
+#define TC_GICD_BASE 0x30000000
+#define TC_GICR_BASE 0x30080000
+#define TC_GICC_BASE 0x2C000000
/* SoC's PL011 UART0 related constants */
#define PL011_UART0_BASE 0x7FF70000
@@ -96,8 +96,8 @@
/* Size of coherent stacks */
#define PCPU_DV_MEM_STACK_SIZE 0x600
-#define PLATFORM_CORE_COUNT (TC0_CLUSTER_COUNT * TC0_MAX_CPUS_PER_CLUSTER)
-#define PLATFORM_NUM_AFFS (TC0_CLUSTER_COUNT + PLATFORM_CORE_COUNT)
+#define PLATFORM_CORE_COUNT (TC_CLUSTER_COUNT * TC_MAX_CPUS_PER_CLUSTER)
+#define PLATFORM_NUM_AFFS (TC_CLUSTER_COUNT + PLATFORM_CORE_COUNT)
#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL1
#define PLAT_MAX_PWR_LEVEL PLATFORM_MAX_AFFLVL
diff --git a/plat/arm/tc0/plat_setup.c b/plat/arm/tc/plat_setup.c
similarity index 73%
rename from plat/arm/tc0/plat_setup.c
rename to plat/arm/tc/plat_setup.c
index 0294c91..6ad8287 100644
--- a/plat/arm/tc0/plat_setup.c
+++ b/plat/arm/tc/plat_setup.c
@@ -8,9 +8,9 @@
#include <xlat_tables_v2.h>
static const mmap_region_t mmap[] = {
- MAP_REGION_FLAT(TC0_DEVICE0_BASE, TC0_DEVICE0_SIZE,
+ MAP_REGION_FLAT(TC_DEVICE0_BASE, TC_DEVICE0_SIZE,
MT_DEVICE | MT_RW | MT_NS),
- MAP_REGION_FLAT(TC0_DEVICE1_BASE, TC0_DEVICE1_SIZE,
+ MAP_REGION_FLAT(TC_DEVICE1_BASE, TC_DEVICE1_SIZE,
MT_DEVICE | MT_RW | MT_NS),
MAP_REGION_FLAT(DRAM_BASE, TFTF_BASE - DRAM_BASE,
MT_MEMORY | MT_RW | MT_NS),
@@ -24,5 +24,5 @@
void plat_arm_gic_init(void)
{
- arm_gic_init(TC0_GICC_BASE, TC0_GICD_BASE, TC0_GICR_BASE);
+ arm_gic_init(TC_GICC_BASE, TC_GICD_BASE, TC_GICR_BASE);
}
diff --git a/plat/arm/tc/platform.mk b/plat/arm/tc/platform.mk
new file mode 100644
index 0000000..cec047c
--- /dev/null
+++ b/plat/arm/tc/platform.mk
@@ -0,0 +1,43 @@
+#
+# Copyright (c) 2020-2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Default number of threads per CPU on FVP
+TC_MAX_PE_PER_CPU := 1
+
+# Check the PE per core count
+ifneq ($(TC_MAX_PE_PER_CPU),$(filter $(TC_MAX_PE_PER_CPU),1 2))
+$(error "Incorrect TC_MAX_PE_PER_CPU specified for TC port")
+endif
+
+# Pass FVP_MAX_PE_PER_CPU to the build system
+$(eval $(call add_define,TFTF_DEFINES,TC_MAX_PE_PER_CPU))
+$(eval $(call add_define,NS_BL1U_DEFINES,TC_MAX_PE_PER_CPU))
+$(eval $(call add_define,NS_BL2U_DEFINES,TC_MAX_PE_PER_CPU))
+
+PLAT_INCLUDES += -Iplat/arm/tc/include/
+
+PLAT_SOURCES := drivers/arm/gic/arm_gic_v2v3.c \
+ drivers/arm/gic/gic_v2.c \
+ drivers/arm/gic/gic_v3.c \
+ drivers/arm/sp805/sp805.c \
+ drivers/arm/timer/private_timer.c \
+ drivers/arm/timer/system_timer.c \
+ plat/arm/tc/${ARCH}/plat_helpers.S \
+ plat/arm/tc/plat_setup.c \
+ plat/arm/tc/tc_mem_prot.c \
+ plat/arm/tc/tc_pwr_state.c \
+ plat/arm/tc/tc_topology.c
+
+CACTUS_SOURCES += plat/arm/tc/${ARCH}/plat_helpers.S
+IVY_SOURCES += plat/arm/tc/${ARCH}/plat_helpers.S
+
+PLAT_TESTS_SKIP_LIST := plat/arm/tc/tests_to_skip.txt
+
+ifeq (${USE_NVM},1)
+$(error "USE_NVM is not supported on TC platforms")
+endif
+
+include plat/arm/common/arm_common.mk
diff --git a/plat/arm/tc/tc_mem_prot.c b/plat/arm/tc/tc_mem_prot.c
new file mode 100644
index 0000000..473cf44
--- /dev/null
+++ b/plat/arm/tc/tc_mem_prot.c
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2020-2023, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <platform.h>
+
+#define TC_DRAM1_NS_START (TFTF_BASE + 0x4000000)
+#define TC_DRAM1_NS_SIZE 0x10000000
+
+static const mem_region_t tc_ram_ranges[] = {
+ { TC_DRAM1_NS_START, TC_DRAM1_NS_SIZE }
+};
+
+const mem_region_t *plat_get_prot_regions(int *nelem)
+{
+ *nelem = ARRAY_SIZE(tc_ram_ranges);
+ return tc_ram_ranges;
+}
diff --git a/plat/arm/tc0/tc0_pwr_state.c b/plat/arm/tc/tc_pwr_state.c
similarity index 62%
rename from plat/arm/tc0/tc0_pwr_state.c
rename to plat/arm/tc/tc_pwr_state.c
index 17d3b39..46d952b 100644
--- a/plat/arm/tc0/tc0_pwr_state.c
+++ b/plat/arm/tc/tc_pwr_state.c
@@ -8,26 +8,26 @@
#include <psci.h>
/* State IDs for local power states on SGI platforms. */
-#define TC0_PS_RUN_STATE_ID 0 /* Valid for CPUs and Clusters */
-#define TC0_PS_RETENTION_STATE_ID 1 /* Valid for only CPUs */
-#define TC0_PS_OFF_STATE_ID 2 /* Valid for CPUs and Clusters */
+#define TC_PS_RUN_STATE_ID 0 /* Valid for CPUs and Clusters */
+#define TC_PS_RETENTION_STATE_ID 1 /* Valid for only CPUs */
+#define TC_PS_OFF_STATE_ID 2 /* Valid for CPUs and Clusters */
/* Suspend depth definitions for each power state */
-#define TC0_PS_RUN_DEPTH 0
-#define TC0_PS_RETENTION_DEPTH 1
-#define TC0_PS_OFF_DEPTH 2
+#define TC_PS_RUN_DEPTH 0
+#define TC_PS_RETENTION_DEPTH 1
+#define TC_PS_OFF_DEPTH 2
/* The state property array with details of idle state possible for the core */
static const plat_state_prop_t core_state_prop[] = {
- {TC0_PS_RETENTION_DEPTH, TC0_PS_RETENTION_STATE_ID,
+ {TC_PS_RETENTION_DEPTH, TC_PS_RETENTION_STATE_ID,
PSTATE_TYPE_STANDBY},
- {TC0_PS_OFF_DEPTH, TC0_PS_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN},
+ {TC_PS_OFF_DEPTH, TC_PS_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN},
{0}
};
/* The state property array with details of idle state possible for the cluster */
static const plat_state_prop_t cluster_state_prop[] = {
- {TC0_PS_OFF_DEPTH, TC0_PS_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN},
+ {TC_PS_OFF_DEPTH, TC_PS_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN},
{0}
};
diff --git a/plat/arm/tc0/tc0_topology.c b/plat/arm/tc/tc_topology.c
similarity index 73%
rename from plat/arm/tc0/tc0_topology.c
rename to plat/arm/tc/tc_topology.c
index 9e30b64..389eb1d 100644
--- a/plat/arm/tc0/tc0_topology.c
+++ b/plat/arm/tc/tc_topology.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,7 +11,7 @@
static const struct {
unsigned int cluster_id;
unsigned int cpu_id;
-} tc0_cores[] = {
+} tc_cores[] = {
/* Cluster0: 8 cores*/
{ 0, 0 },
{ 0, 1 },
@@ -29,18 +29,18 @@
* the indices of the CPU power domain nodes it allocates match the linear
* indices returned by plat_core_pos_by_mpidr().
*/
-const unsigned char tc0_pd_tree_desc[] = {
+const unsigned char tc_pd_tree_desc[] = {
/* Number of root nodes */
- TC0_CLUSTER_COUNT,
+ TC_CLUSTER_COUNT,
/* Number of children for the 1st node */
- TC0_MAX_CPUS_PER_CLUSTER,
+ TC_MAX_CPUS_PER_CLUSTER,
/* Number of children for the 2nd node */
- TC0_MAX_CPUS_PER_CLUSTER
+ TC_MAX_CPUS_PER_CLUSTER
};
const unsigned char *tftf_plat_get_pwr_domain_tree_desc(void)
{
- return tc0_pd_tree_desc;
+ return tc_pd_tree_desc;
}
uint64_t tftf_plat_get_mpidr(unsigned int core_pos)
@@ -49,8 +49,8 @@
assert(core_pos < PLATFORM_CORE_COUNT);
- mpid = (uint64_t)make_mpid(tc0_cores[core_pos].cluster_id,
- tc0_cores[core_pos].cpu_id);
+ mpid = (uint64_t)make_mpid(tc_cores[core_pos].cluster_id,
+ tc_cores[core_pos].cpu_id);
return mpid;
}
diff --git a/plat/arm/tc0/tests_to_skip.txt b/plat/arm/tc/tests_to_skip.txt
similarity index 100%
rename from plat/arm/tc0/tests_to_skip.txt
rename to plat/arm/tc/tests_to_skip.txt
diff --git a/plat/arm/tc0/platform.mk b/plat/arm/tc0/platform.mk
deleted file mode 100644
index 1cfe9ee..0000000
--- a/plat/arm/tc0/platform.mk
+++ /dev/null
@@ -1,43 +0,0 @@
-#
-# Copyright (c) 2020, Arm Limited. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-# Default number of threads per CPU on FVP
-TC0_MAX_PE_PER_CPU := 1
-
-# Check the PE per core count
-ifneq ($(TC0_MAX_PE_PER_CPU),$(filter $(TC0_MAX_PE_PER_CPU),1 2))
-$(error "Incorrect TC0_MAX_PE_PER_CPU specified for TC0 port")
-endif
-
-# Pass FVP_MAX_PE_PER_CPU to the build system
-$(eval $(call add_define,TFTF_DEFINES,TC0_MAX_PE_PER_CPU))
-$(eval $(call add_define,NS_BL1U_DEFINES,TC0_MAX_PE_PER_CPU))
-$(eval $(call add_define,NS_BL2U_DEFINES,TC0_MAX_PE_PER_CPU))
-
-PLAT_INCLUDES += -Iplat/arm/tc0/include/
-
-PLAT_SOURCES := drivers/arm/gic/arm_gic_v2v3.c \
- drivers/arm/gic/gic_v2.c \
- drivers/arm/gic/gic_v3.c \
- drivers/arm/sp805/sp805.c \
- drivers/arm/timer/private_timer.c \
- drivers/arm/timer/system_timer.c \
- plat/arm/tc0/${ARCH}/plat_helpers.S \
- plat/arm/tc0/plat_setup.c \
- plat/arm/tc0/tc0_mem_prot.c \
- plat/arm/tc0/tc0_pwr_state.c \
- plat/arm/tc0/tc0_topology.c
-
-CACTUS_SOURCES += plat/arm/tc0/${ARCH}/plat_helpers.S
-IVY_SOURCES += plat/arm/tc0/${ARCH}/plat_helpers.S
-
-PLAT_TESTS_SKIP_LIST := plat/arm/tc0/tests_to_skip.txt
-
-ifeq (${USE_NVM},1)
-$(error "USE_NVM is not supported on TC0 platforms")
-endif
-
-include plat/arm/common/arm_common.mk
diff --git a/plat/arm/tc0/tc0_mem_prot.c b/plat/arm/tc0/tc0_mem_prot.c
deleted file mode 100644
index 06a333e..0000000
--- a/plat/arm/tc0/tc0_mem_prot.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * Copyright (c) 2020, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <platform.h>
-
-#define TC0_DRAM1_NS_START (TFTF_BASE + 0x4000000)
-#define TC0_DRAM1_NS_SIZE 0x10000000
-
-static const mem_region_t tc0_ram_ranges[] = {
- { TC0_DRAM1_NS_START, TC0_DRAM1_NS_SIZE }
-};
-
-const mem_region_t *plat_get_prot_regions(int *nelem)
-{
- *nelem = ARRAY_SIZE(tc0_ram_ranges);
- return tc0_ram_ranges;
-}