feat(gicv5): add GICv5 instructions and register accessors
Change-Id: I1960b6f0a3bf00ae31c0baadd6202e5d3c894600
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index c73c68f..2258c7d 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -111,6 +111,44 @@
#define ICV_PMR_EL1 S3_0_C4_C6_0
/*******************************************************************************
+ * Definitions for CPU system register interface to GICv5
+ ******************************************************************************/
+#define ICC_CR0_EL1 S3_1_C12_C0_1
+#define ICC_PCR_EL1 S3_1_C12_C0_2
+#define ICC_IAFFIDR_EL1 S3_0_C12_C10_5
+#define ICC_ICSR_EL1 S3_0_C12_C10_4
+
+#define ICC_PPI_ENABLER0 S3_0_C12_C10_6
+#define ICC_PPI_ENABLER1 S3_0_C12_C10_7
+
+#define ICC_PPI_CPENDR0 S3_0_C12_C13_4
+#define ICC_PPI_CPENDR1 S3_0_C12_C13_5
+#define ICC_PPI_SPENDR0 S3_0_C12_C13_6
+#define ICC_PPI_SPENDR1 S3_0_C12_C13_7
+
+#define ICC_PPI_CACTIVER0 S3_0_C12_C13_0
+#define ICC_PPI_CACTIVER1 S3_0_C12_C13_1
+#define ICC_PPI_SACTIVER0 S3_0_C12_C13_2
+#define ICC_PPI_SACTIVER1 S3_0_C12_C13_3
+
+#define ICC_PPI_PRIORITYR0 S3_0_C12_C14_0
+#define ICC_PPI_PRIORITYR1 S3_0_C12_C14_1
+#define ICC_PPI_PRIORITYR2 S3_0_C12_C14_2
+#define ICC_PPI_PRIORITYR3 S3_0_C12_C14_3
+#define ICC_PPI_PRIORITYR4 S3_0_C12_C14_4
+#define ICC_PPI_PRIORITYR5 S3_0_C12_C14_5
+#define ICC_PPI_PRIORITYR6 S3_0_C12_C14_6
+#define ICC_PPI_PRIORITYR7 S3_0_C12_C14_7
+#define ICC_PPI_PRIORITYR8 S3_0_C12_C15_0
+#define ICC_PPI_PRIORITYR9 S3_0_C12_C15_1
+#define ICC_PPI_PRIORITYR10 S3_0_C12_C15_2
+#define ICC_PPI_PRIORITYR11 S3_0_C12_C15_3
+#define ICC_PPI_PRIORITYR12 S3_0_C12_C15_4
+#define ICC_PPI_PRIORITYR13 S3_0_C12_C15_5
+#define ICC_PPI_PRIORITYR14 S3_0_C12_C15_6
+#define ICC_PPI_PRIORITYR15 S3_0_C12_C15_7
+
+/*******************************************************************************
* Definitions for EL2 system registers.
******************************************************************************/
#define CNTPOFF_EL2 S3_4_C14_C0_6
diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h
index 76e2431..13b9a4f 100644
--- a/include/lib/aarch64/arch_helpers.h
+++ b/include/lib/aarch64/arch_helpers.h
@@ -89,6 +89,28 @@
__asm__ (#_op " " #_type ", %0" : : "r" (v)); \
}
+/* Define an instruction with an encoding. Useful when no compiler support */
+#define DEFINE_INSN(_op, _type, _op1, _CRn, _CRm, _op2) \
+static inline void _op ## _type(void) \
+{ \
+ __asm__ ("sys " #_op1 ", " #_CRn ", " #_CRm ", " #_op2 : : : "memory"); \
+}
+
+#define DEFINE_INSN_RET(_op, _type, _op1, _CRn, _CRm, _op2) \
+static inline u_register_t _op ## _type(void) \
+{ \
+ u_register_t v; \
+ __asm__ ("sysl %0, " #_op1 ", " #_CRn ", " #_CRm ", " #_op2 : "=r" (v));\
+ return v; \
+}
+
+/* Define an instruction with an encoding. Useful when no compiler support */
+#define DEFINE_INSN_PARAM(_op, _type, _op1, _CRn, _CRm, _op2) \
+static inline void _op ## _type(u_register_t v) \
+{ \
+ __asm__ ("sys " #_op1 ", " #_CRn ", " #_CRm ", " #_op2 ", %0" : : "r" (v));\
+}
+
/*******************************************************************************
* TLB maintenance accessor prototypes
******************************************************************************/
@@ -167,6 +189,25 @@
DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e2r)
DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e3r)
+/*******************************************************************************
+ * GICv5 system instructions for the Current Interrupt Domain
+ ******************************************************************************/
+DEFINE_INSN_PARAM(gic, cddis, 0, c12, c1, 0)
+DEFINE_INSN_PARAM(gic, cden, 0, c12, c1, 1)
+DEFINE_INSN_PARAM(gic, cdpri, 0, c12, c1, 2)
+DEFINE_INSN_PARAM(gic, cdaff, 0, c12, c1, 3)
+DEFINE_INSN_PARAM(gic, cdpend, 0, c12, c1, 4)
+DEFINE_INSN_PARAM(gic, cdrcfg, 0, c12, c1, 5)
+DEFINE_INSN_RET(gicr, cdia, 0, c12, c3, 0)
+DEFINE_INSN_PARAM(gic, cddi, 0, c12, c2, 0)
+DEFINE_INSN(gic, cdeoi, 0, c12, c1, 7)
+
+/*******************************************************************************
+ * GICv5 barriers
+ ******************************************************************************/
+DEFINE_INSN(gsb, sys, 0, c12, c0, 0)
+DEFINE_INSN(gsb, ack, 0, c12, c0, 1)
+
void flush_dcache_range(uintptr_t addr, size_t size);
void clean_dcache_range(uintptr_t addr, size_t size);
void inv_dcache_range(uintptr_t addr, size_t size);
@@ -520,6 +561,42 @@
DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr1_el0, AMCNTENCLR1_EL0)
DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset1_el0, AMCNTENSET1_EL0)
+/* GICv5 System Registers */
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_cr0_el1, ICC_CR0_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_pcr_el1, ICC_PCR_EL1)
+DEFINE_RENAME_SYSREG_READ_FUNC(icc_iaffidr_el1, ICC_IAFFIDR_EL1)
+DEFINE_RENAME_SYSREG_READ_FUNC(icc_icsr_el1, ICC_ICSR_EL1)
+
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_enabler0, ICC_PPI_ENABLER0)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_enabler1, ICC_PPI_ENABLER1)
+
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_cpendr0, ICC_PPI_CPENDR0)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_cpendr1, ICC_PPI_CPENDR1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_spendr0, ICC_PPI_SPENDR0)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_spendr1, ICC_PPI_SPENDR1)
+
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_cactiver0, ICC_PPI_CACTIVER0)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_cactiver1, ICC_PPI_CACTIVER1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_sactiver0, ICC_PPI_SACTIVER0)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_sactiver1, ICC_PPI_SACTIVER1)
+
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_priorityr0, ICC_PPI_PRIORITYR0)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_priorityr1, ICC_PPI_PRIORITYR1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_priorityr2, ICC_PPI_PRIORITYR2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_priorityr3, ICC_PPI_PRIORITYR3)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_priorityr4, ICC_PPI_PRIORITYR4)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_priorityr5, ICC_PPI_PRIORITYR5)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_priorityr6, ICC_PPI_PRIORITYR6)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_priorityr7, ICC_PPI_PRIORITYR7)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_priorityr8, ICC_PPI_PRIORITYR8)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_priorityr9, ICC_PPI_PRIORITYR9)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_priorityr10, ICC_PPI_PRIORITYR10)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_priorityr11, ICC_PPI_PRIORITYR11)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_priorityr12, ICC_PPI_PRIORITYR12)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_priorityr13, ICC_PPI_PRIORITYR13)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_priorityr14, ICC_PPI_PRIORITYR14)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_priorityr15, ICC_PPI_PRIORITYR15)
+
/* Armv8.4 Memory Partitioning and Monitoring Extension Registers */
DEFINE_RENAME_SYSREG_READ_FUNC(mpamidr_el1, MPAMIDR_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(mpam3_el3, MPAM3_EL3)