feat(neoverse_rd): deprecate and remove NRD1 platform includes
As NRD1 platforms have been removed, remove common includes for
NRD1 platforms.
Change-Id: I0805fc135837b2257b51d9a21dd678178b5df8e2
Signed-off-by: Jerry Wang <Jerry.Wang4@arm.com>
diff --git a/plat/arm/neoverse_rd/common/include/nrd1/nrd_css_def1.h b/plat/arm/neoverse_rd/common/include/nrd1/nrd_css_def1.h
deleted file mode 100644
index 2668c62..0000000
--- a/plat/arm/neoverse_rd/common/include/nrd1/nrd_css_def1.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * This file is limited to include the CSS specific memory and interrupt map
- * definitions for the first generation platforms based on the A75, N1 and V1
- * CPUs. There are minor differences in the memory map of these platforms and
- * those differences are not in the scope of this file.
- */
-
-#ifndef NRD_CSS_DEF1_H
-#define NRD_CSS_DEF1_H
-
-/*******************************************************************************
- * CSS memory map related defines
- ******************************************************************************/
-
-/* Sub-system Peripherals */
-#define NRD_CSS_PERIPH0_BASE UL(0x2A000000)
-#define NRD_CSS_PERIPH0_SIZE UL(0x26000000)
-
-/* Peripherals and PCIe expansion area */
-#define NRD_CSS_PERIPH1_BASE UL(0x60000000)
-#define NRD_CSS_PERIPH1_SIZE UL(0x20000000)
-
-/* DRAM base address and size */
-#define NRD_CSS_DRAM1_BASE UL(0x80000000)
-#define NRD_CSS_DRAM1_SIZE UL(0x80000000)
-
-/* AP Non-Secure UART related constants */
-#define NRD_CSS_NSEC_UART_BASE UL(0x2A400000)
-
-/* Base address of trusted watchdog */
-#define NRD_CSS_TWDOG_BASE UL(0x2A480000)
-
-/* Base address of non-trusted watchdog */
-#define NRD_CSS_WDOG_BASE UL(0x1C0F0000)
-
-/* Memory mapped Generic timer interfaces */
-#define NRD_CSS_NSEC_CNT_BASE1 UL(0x2A830000)
-
-#endif /* NRD_CSS_DEF1_H */
\ No newline at end of file
diff --git a/plat/arm/neoverse_rd/common/include/nrd1/nrd_css_fw_def1.h b/plat/arm/neoverse_rd/common/include/nrd1/nrd_css_fw_def1.h
deleted file mode 100644
index 55356e6..0000000
--- a/plat/arm/neoverse_rd/common/include/nrd1/nrd_css_fw_def1.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * This file is limited to include the CSS firmware specific definitions for
- * the first generation platforms based on the A75, N1 and V1 CPUs.
- */
-
-#ifndef NRD1_CSS_FW_DEF1_H
-#define NRD1_CSS_FW_DEF1_H
-
-#include "nrd_css_def1.h"
-
-/*******************************************************************************
- * Console config
- ******************************************************************************/
-
-#define NRD_CSS_NSEC_CLK_IN_HZ UL(7372800)
-
-#endif /* NRD_CSS_FW_DEF1_H */
\ No newline at end of file
diff --git a/plat/arm/neoverse_rd/common/include/nrd1/nrd_plat_arm_def1.h b/plat/arm/neoverse_rd/common/include/nrd1/nrd_plat_arm_def1.h
deleted file mode 100644
index 6a5085f..0000000
--- a/plat/arm/neoverse_rd/common/include/nrd1/nrd_plat_arm_def1.h
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * This file is limited to include the platform port definitions for the
- * first generation platforms based on the A75, N1 and V1 CPUs.
- */
-
-#ifndef NRD_PLAT_ARM_DEF1_H
-#define NRD_PLAT_ARM_DEF1_H
-
-#ifndef __ASSEMBLER__
-#include <lib/mmio.h>
-#endif /* __ASSEMBLER__ */
-
-#include <lib/utils_def.h>
-#include "nrd_css_fw_def1.h"
-#include "nrd_ros_def1.h"
-
-/*******************************************************************************
- * Linker related definitions
- ******************************************************************************/
-
-/* Platform binary types for linking */
-#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
-#define PLATFORM_LINKER_ARCH aarch64
-
-/*******************************************************************************
- * Stack size
- ******************************************************************************/
-
-/* Size of cacheable stacks */
-#define PLATFORM_STACK_SIZE U(0x1400) /* 5120 bytes */
-
-/* Size of coherent stacks */
-#define PCPU_DV_MEM_STACK_SIZE U(0x600) /* 1536 bytes */
-
-/*******************************************************************************
- * Core count
- ******************************************************************************/
-
-#define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \
- NRD_MAX_CPUS_PER_CLUSTER)
-#define PLATFORM_NUM_AFFS (PLAT_ARM_CLUSTER_COUNT + \
- PLATFORM_CORE_COUNT)
-
-/*******************************************************************************
- * Power related definitions
- ******************************************************************************/
-
-#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL1
-
-#define PLAT_MAX_PWR_LEVEL PLATFORM_MAX_AFFLVL
-#define PLAT_MAX_PWR_STATES_PER_LVL U(2)
-
-/* Local state bit width for each level in the state-ID field of power state */
-#define PLAT_LOCAL_PSTATE_WIDTH U(4)
-
-/*******************************************************************************
- * XLAT definitions
- ******************************************************************************/
-
-/* Platform specific page table and MMU setup constants */
-#define MAX_XLAT_TABLES U(6)
-#define MAX_MMAP_REGIONS U(16)
-
-/*******************************************************************************
- * I/O definitions
- ******************************************************************************/
-
-/* I/O Storage NOR flash device */
-#define MAX_IO_DEVICES U(1)
-#define MAX_IO_HANDLES U(1)
-
-/*******************************************************************************
- * Non-Secure Software Generated Interupts IDs
- ******************************************************************************/
-
-/* Non-Secure Software Generated Interupts IDs */
-#define IRQ_NS_SGI_0 U(0)
-#define IRQ_NS_SGI_7 U(7)
-
-/* Maximum SPI */
-#define PLAT_MAX_SPI_OFFSET_ID U(64)
-
-/*******************************************************************************
- * Timer related config
- ******************************************************************************/
-
-/* Per-CPU Hypervisor Timer Interrupt ID */
-#define IRQ_PCPU_HP_TIMER U(26)
-
-/* Memory mapped Generic timer interfaces */
-#define SYS_CNT_BASE1 NRD_CSS_NSEC_CNT_BASE1
-
-/* AP_REFCLK Generic Timer, Non-secure. */
-#define IRQ_CNTPSIRQ1 U(92)
-
-/* Times(in ms) used by test code for completion of different events */
-#define PLAT_SUSPEND_ENTRY_TIME U(15)
-#define PLAT_SUSPEND_ENTRY_EXIT_TIME U(30)
-
-/*******************************************************************************
- * Console config
- ******************************************************************************/
-
-#define PLAT_ARM_UART_BASE NRD_CSS_NSEC_UART_BASE
-#define PLAT_ARM_UART_CLK_IN_HZ NRD_CSS_NSEC_CLK_IN_HZ
-
-/*******************************************************************************
- * DRAM config
- ******************************************************************************/
-
-/* TF-A reserves DRAM space 0xFF000000- 0xFFFFFFFF for TZC */
-#define DRAM_BASE NRD_CSS_DRAM1_BASE
-#define DRAM_SIZE (NRD_CSS_DRAM1_SIZE - 0x1000000)
-
-/*******************************************************************************
- * Cache related config
- ******************************************************************************/
-
-#define CACHE_WRITEBACK_SHIFT U(6)
-#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
-
-/*******************************************************************************
- * Run-time address of the TFTF image.
- * It has to match the location where the Trusted Firmware-A loads the BL33
- * image.
- ******************************************************************************/
-
-#define TFTF_BASE UL(0xE0000000)
-
-/*******************************************************************************
- * TFTF NVM configs
- ******************************************************************************/
-
-#define TFTF_NVM_OFFSET U(0x0)
-#define TFTF_NVM_SIZE UL(0x08000000) /* 128 MB */
-
-/*******************************************************************************
- * Watchdog related config
- ******************************************************************************/
-
-/* Base address of trusted watchdog (SP805) */
-#define SP805_TWDOG_BASE NRD_CSS_TWDOG_BASE
-
-/* Base address of non-trusted watchdog (SP805) */
-#define SP805_WDOG_BASE NRD_CSS_WDOG_BASE
-
-/* Trusted watchdog (SP805) Interrupt ID */
-#define IRQ_TWDOG_INTID U(86)
-
-/*******************************************************************************
- * Flash related config
- ******************************************************************************/
-
-/* Base address and size of external NVM flash */
-#define FLASH_BASE NRD_ROS_FLASH_BASE
-#define FLASH_SIZE NRD_ROS_FLASH_SIZE
-#define NOR_FLASH_BLOCK_SIZE UL(0x40000) /* 256KB */
-
-#endif /* NRD_PLAT_ARM_DEF1_H */
\ No newline at end of file
diff --git a/plat/arm/neoverse_rd/common/include/nrd1/nrd_ros_def1.h b/plat/arm/neoverse_rd/common/include/nrd1/nrd_ros_def1.h
deleted file mode 100644
index 3c1764b..0000000
--- a/plat/arm/neoverse_rd/common/include/nrd1/nrd_ros_def1.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * This file is limited to include the RoS specific definitions for the first
- * generation platforms based on the A75, N1 and V1 CPUs. RoS (Rest Of System)
- * is used to refer to the part of the reference design platform that excludes
- * CSS.
- */
-
-#ifndef NRD_ROS_DEF1_H
-#define NRD_ROS_DEF1_H
-
-/*******************************************************************************
- * ROS configs
- ******************************************************************************/
-
-/* Base address and size of external NVM flash */
-#define NRD_ROS_FLASH_BASE UL(0x08000000) /* 128MB */
-#define NRD_ROS_FLASH_SIZE UL(0x04000000) /* 64MB */
-
-#endif /* NRD_ROS_DEF1_H */
\ No newline at end of file