fix(versal2): correct SLCR base for timer interrupt
TSP suspend/resume tests were failing because the timer interrupt did
not occur after registration, due to an incorrect SLCR (System Level
Control Registers) base address mapping.
Updated the SLCR base address to align with the AMD Versal Gen 2
register mapping and configured the TTC (Triple Timer Counter) base
to TTC0.
Change-Id: I64e3bbed20e440a8fd6f26295ee72ef421392360
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>
1 file changed