tree a50ccb99f9389255d0dc158df40e5a0ace067451
parent 32815d30b1d4b2126cdff5ef9908446e1880d44e
author Boyan Karatotev <boyan.karatotev@arm.com> 1747830340 +0100
committer Boyan Karatotev <boyan.karatotev@arm.com> 1753176172 +0100

fix(sme): update smcr_el2 after hcr_el2 has taken effect

If HCR_EL2.E2H resets to 1 and its write to 0 is delayed by the lack of
isb, then the SMCR_EL2 access will trap as CPTR_EL2.SMEN will dictate
the trapping behaviour and we leave it at 0.

Write hcr_el2 with the other registers so there's an isb between its
write and the access to smcr_el2.

Change-Id: Ia4f546a070d7f9d5e3cd330979e6587606fffcdf
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>