fix(sme): update smcr_el2 after hcr_el2 has taken effect
If HCR_EL2.E2H resets to 1 and its write to 0 is delayed by the lack of
isb, then the SMCR_EL2 access will trap as CPTR_EL2.SMEN will dictate
the trapping behaviour and we leave it at 0.
Write hcr_el2 with the other registers so there's an isb between its
write and the access to smcr_el2.
Change-Id: Ia4f546a070d7f9d5e3cd330979e6587606fffcdf
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
diff --git a/lib/power_management/suspend/aarch64/asm_tftf_suspend.S b/lib/power_management/suspend/aarch64/asm_tftf_suspend.S
index 770a1bd..83df3fb 100644
--- a/lib/power_management/suspend/aarch64/asm_tftf_suspend.S
+++ b/lib/power_management/suspend/aarch64/asm_tftf_suspend.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -125,11 +125,13 @@
ldp x1, x2, [x0, #SUSPEND_CTX_MAIR_OFFSET]
ldp x3, x4, [x0, #SUSPEND_CTX_TTBR0_OFFSET]
ldp x5, x6, [x0, #SUSPEND_CTX_VBAR_OFFSET]
+ ldr x7, [x0, #SUSPEND_CTX_HCR_OFFSET]
msr mair_el2, x1
msr cptr_el2, x2
msr ttbr0_el2, x3
msr tcr_el2, x4
msr vbar_el2, x5
+ msr hcr_el2, x7
/* make sure whatever just got turned on is in effect */
isb
@@ -138,13 +140,9 @@
*/
mrs x2, id_aa64pfr1_el1
tst x2, #(1 << 25)
- bne 3f
- ldr x1, [x0, #SUSPEND_CTX_HCR_OFFSET]
- msr hcr_el2, x1
- b 4f
+ beq 4f
-3: ldp x1, x2, [x0, #SUSPEND_CTX_HCR_OFFSET]
- msr hcr_el2, x1
+ ldr x2, [x0, #SUSPEND_CTX_SMCR_OFFSET]
msr SMCR_EL2, x2
/*
diff --git a/lib/power_management/suspend/suspend_private.h b/lib/power_management/suspend/suspend_private.h
index debd84f..c91153d 100644
--- a/lib/power_management/suspend/suspend_private.h
+++ b/lib/power_management/suspend/suspend_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -25,6 +25,7 @@
#define SUSPEND_CTX_TTBR0_OFFSET 16
#define SUSPEND_CTX_VBAR_OFFSET 32
#define SUSPEND_CTX_HCR_OFFSET 48
+#define SUSPEND_CTX_SMCR_OFFSET 56
#define SUSPEND_CTX_APIAKEY_OFFSET 64
#define SUSPEND_CTX_SP_OFFSET (8 * NR_CTX_REGS)