refactor(xilinx): mark ttc clock select platform specific
TTC clock select register(TTC_CLK_SEL) is used to select
TTC reference clock.
The offset for TTC_CLK_SEL in LPD_IOU_SLCR register module
differs on various AMD xilinx platforms.
Offset is 0x380 for zynqmp platform and is 0x360 for versal
and versal-net platforms.
According define offset for TTC clock select in platform
specific files.
Change-Id: I479f655704fcc515068425eedc5d73d24a32dde0
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
diff --git a/plat/xilinx/common/timer/timers.c b/plat/xilinx/common/timer/timers.c
index a6e1afa..f53cd84 100644
--- a/plat/xilinx/common/timer/timers.c
+++ b/plat/xilinx/common/timer/timers.c
@@ -27,7 +27,6 @@
#define TTC_CNT_CNTRL_DISABLE_MASK BIT(0)
-#define TTC_CLK_SEL_OFFSET U(0x360)
#define TTC_CLK_SEL_MASK GENMASK(1, 0)
#define TTC_CLK_SEL_PS_REF BIT(0)
diff --git a/plat/xilinx/versal/include/platform_def.h b/plat/xilinx/versal/include/platform_def.h
index 925825c..73b6db2 100644
--- a/plat/xilinx/versal/include/platform_def.h
+++ b/plat/xilinx/versal/include/platform_def.h
@@ -116,5 +116,6 @@
#define IRQ_TWDOG_INTID U(0x51)
#define TTC_TIMER_IRQ U(69)
+#define TTC_CLK_SEL_OFFSET U(0x360)
#endif /* PLATFORM_DEF_H */
diff --git a/plat/xilinx/versal_net/include/platform_def.h b/plat/xilinx/versal_net/include/platform_def.h
index 8431ca6..92a7ba0 100644
--- a/plat/xilinx/versal_net/include/platform_def.h
+++ b/plat/xilinx/versal_net/include/platform_def.h
@@ -122,5 +122,6 @@
#define IRQ_TWDOG_INTID U(0x51)
#define TTC_TIMER_IRQ U(75)
+#define TTC_CLK_SEL_OFFSET U(0x360)
#endif /* PLATFORM_DEF_H */