plat: tc0: set PLAT_CACTUS_CORE_COUNT, disable SMMUv3 tests
Define platform specific SMMUv3 test driver macros. These macros will
be set to proper values once SMMUv3 is enabled for TC platform.
Disables SMMUv3 tests.
Enables PSCI NODE_HW_STATE API test.
Change-Id: I1bd0f362521d892d4b33a2188bf8c5065c45d6f0
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
diff --git a/plat/arm/tc0/include/platform_def.h b/plat/arm/tc0/include/platform_def.h
index def4154..9df99d1 100644
--- a/plat/arm/tc0/include/platform_def.h
+++ b/plat/arm/tc0/include/platform_def.h
@@ -109,7 +109,12 @@
/* Platform specific page table and MMU setup constants */
#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 36)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 36)
+
+#if IMAGE_CACTUS
+#define MAX_XLAT_TABLES 6
+#else
#define MAX_XLAT_TABLES 5
+#endif
#define MAX_MMAP_REGIONS 16
/*******************************************************************************
diff --git a/plat/arm/tc0/tests_to_skip.txt b/plat/arm/tc0/tests_to_skip.txt
index f039eed..0d1c16d 100644
--- a/plat/arm/tc0/tests_to_skip.txt
+++ b/plat/arm/tc0/tests_to_skip.txt
@@ -4,9 +4,9 @@
# SPDX-License-Identifier: BSD-3-Clause
#
-# System suspend is not supported as there are no wakeup sources in tc0 FVP
+# Disable SMMUv3 tests
+SMMUv3 tests
# PSCI is enabled but not tested
PSCI STAT/Stats test cases after system suspend
PSCI System Suspend Validation
-PSCI NODE_HW_STATE
diff --git a/spm/cactus/plat/arm/tc0/include/cactus_platform_def.h b/spm/cactus/plat/arm/tc0/include/cactus_platform_def.h
index 42dd291..585391d 100644
--- a/spm/cactus/plat/arm/tc0/include/cactus_platform_def.h
+++ b/spm/cactus/plat/arm/tc0/include/cactus_platform_def.h
@@ -16,9 +16,20 @@
#define CACTUS_PL011_UART_CLK_IN_HZ PL011_UART1_CLK_IN_HZ
#define PLAT_CACTUS_RX_BASE ULL(0xfe300000)
+#define PLAT_CACTUS_CORE_COUNT (8)
#define CACTUS_PRIMARY_EC_COUNT (8U)
#define CACTUS_SECONDARY_EC_COUNT (8U)
#define CACTUS_TERTIARY_EC_COUNT (1U)
+/* Scratch memory used for SMMUv3 driver testing purposes in Cactus SP */
+/* SMMUv3 tests are disabled for TC platform */
+#define PLAT_CACTUS_MEMCPY_BASE ULL(0xfe400000)
+#define PLAT_CACTUS_MEMCPY_RANGE ULL(0x8000)
+
+/* Base address of user and PRIV frames in SMMUv3TestEngine */
+/* SMMUv3 tests are disabled for TC platform */
+#define USR_BASE_FRAME ULL(0x0)
+#define PRIV_BASE_FRAME ULL(0x0)
+
#endif /* CACTUS_PLATFORM_DEF_H */