Minor bug fixes in multicore IRQ spurious test
Program the memory mapped GIC_ITARGETSR register with appropriate
cpu mask and assert the expected value is returned upon reading
the register.
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Change-Id: I356111d763569c229d7f4c9ea3cd4899305a4954
diff --git a/include/drivers/arm/gic_v2.h b/include/drivers/arm/gic_v2.h
index 8432a3f..6e7b764 100644
--- a/include/drivers/arm/gic_v2.h
+++ b/include/drivers/arm/gic_v2.h
@@ -242,6 +242,11 @@
unsigned int gicv2_gicc_read_iar(void);
/*
+ * Read and return the target core mask of interrupt ID `num`.
+ */
+uint8_t gicv2_read_itargetsr_value(unsigned int num);
+
+/*
* Set the bit corresponding to `num` in the GICD ICENABLER register.
*/
void gicv2_gicd_set_icenabler(unsigned int num);