Merge "fix(fwu): invalidate the data cache for NS_BL1U and NS_BL2U images"
diff --git a/fwu/ns_bl1u/aarch32/ns_bl1u_entrypoint.S b/fwu/ns_bl1u/aarch32/ns_bl1u_entrypoint.S
index b9c0d87..74c5600 100644
--- a/fwu/ns_bl1u/aarch32/ns_bl1u_entrypoint.S
+++ b/fwu/ns_bl1u/aarch32/ns_bl1u_entrypoint.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2021, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -28,6 +28,17 @@
stcopr r0, HSCTLR
isb
+ /* --------------------------------------------------------------------
+ * Invalidate the cache in the RW memory range to safeguard
+ * against possible stale data in the cache from previous
+ * firmware stage.
+ * --------------------------------------------------------------------
+ */
+ ldr r0, =__RW_START__
+ ldr r1, =__RW_END__
+ sub r1, r1, r0
+ bl inv_dcache_range
+
/* ---------------------------------------------------------------------
* Init C runtime environment.
* - Zero-initialise the .bss section;
@@ -48,8 +59,6 @@
* Allocate a stack whose memory will be marked as Normal
* Inner-Shareable, Write-Back, Write-Allocate memory when the MMU is
* enabled.
- * There is no risk of reading stale stack memory after enabling the MMU
- * as only the primary CPU is running at the moment.
* ---------------------------------------------------------------------
*/
ldcopr r0, MPIDR
diff --git a/fwu/ns_bl1u/aarch64/ns_bl1u_entrypoint.S b/fwu/ns_bl1u/aarch64/ns_bl1u_entrypoint.S
index d971e4a..a73435b 100644
--- a/fwu/ns_bl1u/aarch64/ns_bl1u_entrypoint.S
+++ b/fwu/ns_bl1u/aarch64/ns_bl1u_entrypoint.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2021, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -28,6 +28,17 @@
asm_write_sctlr_el1_or_el2 x1
isb
+ /* --------------------------------------------------------------------
+ * Invalidate the cache in the RW memory range to safeguard
+ * against possible stale data in the cache from previous
+ * firmware stage.
+ * --------------------------------------------------------------------
+ */
+ ldr x0, =__RW_START__
+ ldr x1, =__RW_END__
+ sub x1, x1, x0
+ bl inv_dcache_range
+
/* ---------------------------------------------------------------------
* Init C runtime environment.
* - Zero-initialise the .bss section;
@@ -48,8 +59,6 @@
* Allocate a stack whose memory will be marked as Normal
* Inner-Shareable, Write-Back, Write-Allocate memory when the MMU is
* enabled.
- * There is no risk of reading stale stack memory after enabling the MMU
- * as only the primary CPU is running at the moment.
* ---------------------------------------------------------------------
*/
mrs x0, mpidr_el1
diff --git a/fwu/ns_bl1u/ns_bl1u.ld.S b/fwu/ns_bl1u/ns_bl1u.ld.S
index 52d80de..5021daf 100644
--- a/fwu/ns_bl1u/ns_bl1u.ld.S
+++ b/fwu/ns_bl1u/ns_bl1u.ld.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2021, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -43,6 +43,7 @@
* Its VMA must be page-aligned as it marks the first read/write page.
*/
. = NS_BL1U_RW_BASE;
+ __RW_START__ = .;
ASSERT(. == ALIGN(PAGE_SIZE),
"NS_BL1U_RW_BASE address is not aligned on a page boundary.")
.data . : ALIGN(16) {
@@ -79,6 +80,7 @@
__NS_BL1U_RAM_START__ = ADDR(.data);
__NS_BL1U_RAM_END__ = .;
+ __RW_END__ = .;
__DATA_ROM_START__ = LOADADDR(.data);
__DATA_SIZE__ = SIZEOF(.data);
diff --git a/fwu/ns_bl2u/aarch32/ns_bl2u_entrypoint.S b/fwu/ns_bl2u/aarch32/ns_bl2u_entrypoint.S
index 28a4572..7611642 100644
--- a/fwu/ns_bl2u/aarch32/ns_bl2u_entrypoint.S
+++ b/fwu/ns_bl2u/aarch32/ns_bl2u_entrypoint.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2021, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -28,6 +28,17 @@
stcopr r0, HSCTLR
isb
+ /* --------------------------------------------------------------------
+ * Invalidate the cache in the RW memory range to safeguard
+ * against possible stale data in the cache from previous
+ * firmware stage.
+ * --------------------------------------------------------------------
+ */
+ ldr r0, =__RW_START__
+ ldr r1, =__RW_END__
+ sub r1, r1, r0
+ bl inv_dcache_range
+
/* ---------------------------------------------------------------------
* Zero-initialise the .bss section.
* ---------------------------------------------------------------------
@@ -40,8 +51,6 @@
* Allocate a stack whose memory will be marked as Normal
* Inner-Shareable, Write-Back, Write-Allocate memory when the MMU is
* enabled.
- * There is no risk of reading stale stack memory after enabling the MMU
- * as only the primary CPU is running at the moment.
* ---------------------------------------------------------------------
*/
ldcopr r0, MPIDR
diff --git a/fwu/ns_bl2u/aarch64/ns_bl2u_entrypoint.S b/fwu/ns_bl2u/aarch64/ns_bl2u_entrypoint.S
index 28d6dfa..1bc057c 100644
--- a/fwu/ns_bl2u/aarch64/ns_bl2u_entrypoint.S
+++ b/fwu/ns_bl2u/aarch64/ns_bl2u_entrypoint.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2021, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -28,6 +28,17 @@
asm_write_sctlr_el1_or_el2 x1
isb
+ /* --------------------------------------------------------------------
+ * Invalidate the cache in the RW memory range to safeguard
+ * against possible stale data in the cache from previous
+ * firmware stage.
+ * --------------------------------------------------------------------
+ */
+ ldr x0, =__RW_START__
+ ldr x1, =__RW_END__
+ sub x1, x1, x0
+ bl inv_dcache_range
+
/* ---------------------------------------------------------------------
* Zero-initialise the .bss section.
* ---------------------------------------------------------------------
@@ -40,8 +51,6 @@
* Allocate a stack whose memory will be marked as Normal
* Inner-Shareable, Write-Back, Write-Allocate memory when the MMU is
* enabled.
- * There is no risk of reading stale stack memory after enabling the MMU
- * as only the primary CPU is running at the moment.
* ---------------------------------------------------------------------
*/
mrs x0, mpidr_el1
diff --git a/fwu/ns_bl2u/ns_bl2u.ld.S b/fwu/ns_bl2u/ns_bl2u.ld.S
index a6c6d2e..d8949f3 100644
--- a/fwu/ns_bl2u/ns_bl2u.ld.S
+++ b/fwu/ns_bl2u/ns_bl2u.ld.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2021, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -42,6 +42,8 @@
__RODATA_END__ = .;
} >RAM
+ __RW_START__ = .;
+
.data . : {
__DATA_START__ = .;
*(.data*)
@@ -75,6 +77,7 @@
} >RAM
__NS_BL2U_END__ = .;
+ __RW_END__ = .;
__BSS_SIZE__ = SIZEOF(.bss);