Merge changes from topic "xlnx_versal2_tftf_base"
* changes:
fix(versal2): update test skip list
fix(versal2): update tftf and uart base address
diff --git a/plat/amd/versal2/include/platform_def.h b/plat/amd/versal2/include/platform_def.h
index 61392a7..89a8cde 100644
--- a/plat/amd/versal2/include/platform_def.h
+++ b/plat/amd/versal2/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2024, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2024-2025, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -12,7 +12,7 @@
#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
#define PLATFORM_LINKER_ARCH aarch64
-#define TFTF_BASE U(0x8000000)
+#define TFTF_BASE U(0x40000000)
#define CACHE_WRITEBACK_GRANULE U(0x40)
@@ -77,13 +77,14 @@
/* ARM PL011 UART */
#define PL011_UART0_BASE U(0xf1920000)
+#define PL011_UART1_BASE U(0xf1930000)
#define PL011_BAUDRATE U(115200)
#define PL011_UART_CLK_IN_HZ U(100000000)
-#define PLAT_ARM_UART_BASE PL011_UART0_BASE
+#define PLAT_ARM_UART_BASE PL011_UART1_BASE
#define PLAT_ARM_UART_SIZE U(0x1000)
-#define CRASH_CONSOLE_BASE PL011_UART0_BASE
+#define CRASH_CONSOLE_BASE PL011_UART1_BASE
#define CRASH_CONSOLE_SIZE PLAT_ARM_UART_SIZE
/*******************************************************************************
diff --git a/plat/amd/versal2/tests_to_skip.txt b/plat/amd/versal2/tests_to_skip.txt
index 2c286ec..3179879 100644
--- a/plat/amd/versal2/tests_to_skip.txt
+++ b/plat/amd/versal2/tests_to_skip.txt
@@ -33,6 +33,7 @@
SIMD,SVE Registers context/Check that SIMD registers context is preserved
FF-A Interrupt
FF-A Notifications
+FF-A Group0 interrupts/FF-A Group0 normal world
#TESTS: AMD-Xilinx tests
AMD-Xilinx tests
@@ -47,10 +48,12 @@
PSCI CPU Suspend/CPU suspend to standby at level 2
PSCI CPU Suspend in OSI mode/CPU suspend to powerdown at level 0 in OSI mode
PSCI CPU Suspend in OSI mode/CPU suspend to powerdown at level 1 in OSI mode
+CPU Hotplug/Invalid entry point
PSCI System Suspend Validation/System suspend multiple times
PSCI System Suspend Validation/system suspend from all cores
PSCI System Suspend Validation/Validate suspend to RAM functionality
PSCI System Suspend Validation/Validate PSCI System Suspend API
+PSCI System Suspend Validation/Suspend system with cores in suspend
#PSCI
PSCI Features