feat(afp): add a test for Advanced floating-point
This test is to ensure that TFTF is allowed to write the FPCR register
bits to control the floating-point operation when FEAT_AFP is
implemented.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I21ea288e698bbe706aac55740e28d5f6ccb700dc
diff --git a/tftf/tests/tests-cpu-extensions.xml b/tftf/tests/tests-cpu-extensions.xml
index 3d18f84..97826cc 100644
--- a/tftf/tests/tests-cpu-extensions.xml
+++ b/tftf/tests/tests-cpu-extensions.xml
@@ -25,6 +25,7 @@
<testcase name="Use trace system Registers" function="test_sys_reg_trace_enabled" />
<testcase name="SME support" function="test_sme_support" />
<testcase name="SPE support" function="test_spe_support" />
+ <testcase name="AFP support" function="test_afp_support" />
</testsuite>
<testsuite name="ARM_ARCH_SVC" description="Arm Architecture Service tests">