feat: test if errata 2938996 and 2726228 workaround is applied
This patch confirms if access to trbe el1 register generates an undef
injection in affected cores. If a core is affected by errata 2938996/
2726228 and it generates an undef injection on access to trbe el1 register then
the test passes. If it is an unaffected core then the test passes , but
when undef injection doesn't happen in affected core, the test fails.
Change-Id: I515a9aa4613c6d99ee73e579206089ebf89ffae8
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
diff --git a/include/common/test_helpers.h b/include/common/test_helpers.h
index 3caca39..d6a7ade 100644
--- a/include/common/test_helpers.h
+++ b/include/common/test_helpers.h
@@ -420,4 +420,9 @@
/* Generate 64-bit random number */
unsigned long long rand64(void);
+/* TRBE Errata */
+#define CORTEX_A520_MIDR U(0x410FD800)
+#define CORTEX_X4_MIDR U(0x410FD821)
+#define RXPX_RANGE(x, y, z) (((x >= y) && (x <= z)) ? true : false)
+bool is_trbe_errata_affected_core(void);
#endif /* __TEST_HELPERS_H__ */
diff --git a/include/lib/aarch32/arch.h b/include/lib/aarch32/arch.h
index 6f41db9..cfbce56 100644
--- a/include/lib/aarch32/arch.h
+++ b/include/lib/aarch32/arch.h
@@ -23,6 +23,16 @@
#define MIDR_VAR_MASK U(0xf0)
#define MIDR_REV_MASK U(0xf)
+/******************************************************************************
+ * MIDR macros
+ *****************************************************************************/
+/* Extract the partnumber */
+#define EXTRACT_PARTNUM(x) ((x >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
+/* Extract revision and variant info */
+
+#define EXTRACT_REV_VAR(x) (x & MIDR_REV_MASK) | ((x >> (MIDR_VAR_SHIFT - MIDR_REV_BITS)) \
+ & MIDR_VAR_MASK)
+
/*******************************************************************************
* MPIDR macros
******************************************************************************/
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index c45358e..d29f5a6 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -23,6 +23,16 @@
#define MIDR_PN_MASK U(0xfff)
#define MIDR_PN_SHIFT U(0x4)
+/******************************************************************************
+ * MIDR macros
+ *****************************************************************************/
+/* Extract the partnumber */
+#define EXTRACT_PARTNUM(x) ((x >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
+/* Extract revision and variant info */
+
+#define EXTRACT_REV_VAR(x) (x & MIDR_REV_MASK) | ((x >> (MIDR_VAR_SHIFT - MIDR_REV_BITS)) \
+ & MIDR_VAR_MASK)
+
/*******************************************************************************
* MPIDR macros
******************************************************************************/