feat(zynqmp): introduce platform support
Introduce platform support for AMD-Xilinx zynqmp, an adaptive
compute acceleration platform (ACAP).
- TF-A cadence driver is used for console.
- TTC is used for Timers.
summary:
=================================
Tests Skipped : 193
Tests Passed : 29
Tests Failed : 0
Tests Crashed : 0
Total tests : 222
=================================
NOTICE: Exiting tests.
Change-Id: Ia63df682f8e97cc3a5d88468bf0df71f6bb3fc26
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
diff --git a/include/drivers/cadence/cdns_uart.h b/include/drivers/cadence/cdns_uart.h
new file mode 100644
index 0000000..87e98ea
--- /dev/null
+++ b/include/drivers/cadence/cdns_uart.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CDNS_UART_H
+#define CDNS_UART_H
+
+#include <drivers/console.h>
+#include <lib/utils_def.h>
+/* This is very minimalistic and will only work in QEMU. */
+
+/* CADENCE Registers */
+#define R_UART_CR 0
+#define R_UART_CR_RXRST (1 << 0) /* RX logic reset */
+#define R_UART_CR_TXRST (1 << 1) /* TX logic reset */
+#define R_UART_CR_RX_EN (1 << 2) /* RX enabled */
+#define R_UART_CR_TX_EN (1 << 4) /* TX enabled */
+
+#define R_UART_SR 0x2C
+#define UART_SR_INTR_REMPTY_BIT 1
+#define UART_SR_INTR_TFUL_BIT 4
+#define UART_SR_INTR_TEMPTY_BIT 3
+
+#define R_UART_TX 0x30
+#define R_UART_RX 0x30
+
+#define CONSOLE_T_BASE (U(5) * REGSZ)
+
+#endif /* CDNS_UART_H */