Tegra: timer: define RTC irq number in each platform
The RTC irq number may be different for different platform.
Introduce new macro TEGRA_PLAT_RTC_IRQ to define the platform
RTC irq number.
Signed-off-by: anzhou <anzhou@nvidia.com>
Change-Id: I5b66b9720fb7fe9a71a5b800764635166da9f1ae
diff --git a/plat/nvidia/drivers/timer/timers.c b/plat/nvidia/drivers/timer/timers.c
index e8f359a..f127bb7 100644
--- a/plat/nvidia/drivers/timer/timers.c
+++ b/plat/nvidia/drivers/timer/timers.c
@@ -16,9 +16,6 @@
/* timer granularity in ms */
#define TEGRA_RTC_STEP_VALUE_MS U(5)
-/* IRQ value for Tegra Timer0 */
-#define TEGRA_RTC_IRQ U(42)
-
/* set to 1 = busy every eight 32kHz clocks during copy of sec+msec to AHB */
#define TEGRA_RTC_REG_BUSY U(0x004)
#define TEGRA_RTC_REG_SECONDS U(0x008)
diff --git a/plat/nvidia/tegra186/include/platform_def.h b/plat/nvidia/tegra186/include/platform_def.h
index d746aee..d21d83c 100644
--- a/plat/nvidia/tegra186/include/platform_def.h
+++ b/plat/nvidia/tegra186/include/platform_def.h
@@ -121,6 +121,11 @@
#define IRQ_PCPU_HP_TIMER 26
/*******************************************************************************
+ * IRQ value for Tegra Timer0
+ ******************************************************************************/
+#define TEGRA_RTC_IRQ U(42)
+
+/*******************************************************************************
* Platform specific page table and MMU setup constants
******************************************************************************/
#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 40)
diff --git a/plat/nvidia/tegra194/include/platform_def.h b/plat/nvidia/tegra194/include/platform_def.h
index e580b4d..9b27da3 100644
--- a/plat/nvidia/tegra194/include/platform_def.h
+++ b/plat/nvidia/tegra194/include/platform_def.h
@@ -122,6 +122,11 @@
#define IRQ_PCPU_HP_TIMER 26
/*******************************************************************************
+ * IRQ value for Tegra Timer0
+ ******************************************************************************/
+#define TEGRA_RTC_IRQ U(42)
+
+/*******************************************************************************
* Platform specific page table and MMU setup constants
******************************************************************************/
#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 40)