feat(ls64): add LS64_ACCDATA test
FEAT_LS64_ACCDATA introduces the system register ACCDATA_EL1, its value
replacing the first four bytes of the data provided to an ST64BV0
instruction. As this system register would need context switching
between non-secure and secure worlds, there is an SCR_EL3 bit to allow
trapping accesses from lower ELs into EL3.
Introduce a check to verify that accesses to this system register do not
trap into EL3, if the CPUID registers advertise this feature.
Bits[63:32] of ACCDATA_EL1 are described as RES0, so mask those bits
when comparing the read-back values with the written one.
Change-Id: Ia32bcf7187356c701470a1757708b3d554e88629
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
diff --git a/tftf/tests/tests-cpu-extensions.xml b/tftf/tests/tests-cpu-extensions.xml
index 62bb9ea..34ac0b6 100644
--- a/tftf/tests/tests-cpu-extensions.xml
+++ b/tftf/tests/tests-cpu-extensions.xml
@@ -38,6 +38,7 @@
<testcase name="PMUv3 event counter functional in NS" function="test_pmuv3_event_works_ns" />
<testcase name="PMUv3 SMC counter preservation" function="test_pmuv3_el3_preserves" />
<testcase name="LS64 support" function="test_ls64_instructions" />
+ <testcase name="LS64-ACCDATA support" function="test_ls64_accdata_sysreg" />
</testsuite>
<testsuite name="ARM_ARCH_SVC" description="Arm Architecture Service tests">