refactor: clarify which kind of exceptions it catches
The function that was called "undef_injection_handler" doesn't just
catch undef injections. It also catches traps to EL2 due to registers
not being present. Both cases have the same EC value, so it is
impossible to distinguish between them.
This patch edits variable names and adds a comment to clarify this.
Change-Id: Ie7405d7611afc1d2ff2207cfa4a08de3cbc9dff7
Signed-off-by: Charlie Bareham <charlie.bareham@arm.com>
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
diff --git a/tftf/tests/misc_tests/test_asymmetric_features.c b/tftf/tests/misc_tests/test_asymmetric_features.c
index a202034..322afc0 100644
--- a/tftf/tests/misc_tests/test_asymmetric_features.c
+++ b/tftf/tests/misc_tests/test_asymmetric_features.c
@@ -19,15 +19,20 @@
static event_t cpu_has_entered_test[PLATFORM_CORE_COUNT];
-static volatile bool undef_injection_triggered;
+static volatile bool exception_triggered;
static unsigned int test_result;
-static bool undef_injection_handler(void)
+static bool exception_handler(void)
{
uint64_t esr_el2 = read_esr_el2();
if (EC_BITS(esr_el2) == EC_UNKNOWN) {
- undef_injection_triggered = true;
+ /*
+ * This may be an undef injection, or a trap to EL2 due to a
+ * register not being present. Both cases have the same EC
+ * value.
+ */
+ exception_triggered = true;
return true;
}
@@ -40,16 +45,16 @@
unsigned int core_pos = platform_get_core_pos(mpid);
bool check_if_affected = is_trbe_errata_affected_core();
- register_custom_sync_exception_handler(undef_injection_handler);
- undef_injection_triggered = false;
+ register_custom_sync_exception_handler(exception_handler);
+ exception_triggered = false;
read_trblimitr_el1();
unregister_custom_sync_exception_handler();
- if (undef_injection_triggered == true && check_if_affected == true) {
+ if (exception_triggered == true && check_if_affected == true) {
test_result = TEST_RESULT_SUCCESS;
- tftf_testcase_printf("Undef injection triggered for core = %d "
+ tftf_testcase_printf("Exception triggered for core = %d "
"when accessing TRB_LIMTR\n", core_pos);
- } else if (undef_injection_triggered == false && check_if_affected == false) {
+ } else if (exception_triggered == false && check_if_affected == false) {
test_result = TEST_RESULT_SUCCESS;
tftf_testcase_printf("TRB_LIMITR register accessible for core "
"= %d\n", core_pos);
@@ -65,16 +70,16 @@
unsigned int mpid = read_mpidr_el1() & MPID_MASK;
unsigned int core_pos = platform_get_core_pos(mpid);
- register_custom_sync_exception_handler(undef_injection_handler);
- undef_injection_triggered = false;
+ register_custom_sync_exception_handler(exception_handler);
+ exception_triggered = false;
read_pmscr_el1();
unregister_custom_sync_exception_handler();
- if (undef_injection_triggered == true && !is_feat_spe_supported()) {
+ if (exception_triggered == true && !is_feat_spe_supported()) {
test_result = TEST_RESULT_SUCCESS;
- tftf_testcase_printf("Undef injection triggered for core = %d "
+ tftf_testcase_printf("Exception triggered for core = %d "
"when accessing PMSCR_EL1\n", core_pos);
- } else if (undef_injection_triggered == false &&
+ } else if (exception_triggered == false &&
is_feat_spe_supported()) {
test_result = TEST_RESULT_SUCCESS;
tftf_testcase_printf("PMSCR_EL1 register accessible for core = "