feat(rdn2cfg1): add tftf support
Add tftf support for Neoverse Reference Design RD-N2-Cfg1 platform.
Signed-off-by: Shriram K <shriram.k@arm.com>
Change-Id: I0d9287a50f8e1867e42bc0b0f29e94e9274f5eca
diff --git a/plat/arm/rdinfra/rdn2/include/platform_def.h b/plat/arm/rdinfra/rdn2/include/platform_def.h
index a4bd73c..ab4149d 100644
--- a/plat/arm/rdinfra/rdn2/include/platform_def.h
+++ b/plat/arm/rdinfra/rdn2/include/platform_def.h
@@ -9,13 +9,27 @@
#include <sgi_soc_platform_def_v2.h>
+/*
+ * The RD-N2 Cfg1 platform is a variant of the RD-N2 platform with a
+ * reduced interconnect mesh size (3x3) and core count (8-cores).
+ *
+ * The $CSS_SGI_PLATFORM_VARIANT flag is set to 1 for RD-N2-Cfg1 platform.
+ */
+#if (CSS_SGI_PLATFORM_VARIANT == 1)
+#define PLAT_ARM_CLUSTER_COUNT U(8)
+#else
#define PLAT_ARM_CLUSTER_COUNT U(16)
+#endif
#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(1)
#define CSS_SGI_MAX_PE_PER_CPU U(1)
/* GIC-600 & interrupt handling related constants */
#define PLAT_ARM_GICD_BASE UL(0x30000000)
+#if (CSS_SGI_PLATFORM_VARIANT == 1)
+#define PLAT_ARM_GICR_BASE UL(0x30100000)
+#else
#define PLAT_ARM_GICR_BASE UL(0x301C0000)
+#endif
#define PLAT_ARM_GICC_BASE UL(0x2C000000)
/* Platform specific page table and MMU setup constants */
diff --git a/plat/arm/rdinfra/rdn2/platform.mk b/plat/arm/rdinfra/rdn2/platform.mk
index ed8f252..01f56b3 100644
--- a/plat/arm/rdinfra/rdn2/platform.mk
+++ b/plat/arm/rdinfra/rdn2/platform.mk
@@ -12,7 +12,10 @@
PLAT_TESTS_SKIP_LIST := plat/arm/rdinfra/rdn2/tests_to_skip.txt
-ifneq ($(CSS_SGI_PLATFORM_VARIANT),0)
- $(error "CSS_SGI_PLATFORM_VARIANT for RD-N2 should always be 0, \
- currently set to ${CSS_SGI_PLATFORM_VARIANT}.")
+RD_N2_VARIANTS := 0 1
+
+ifneq ($(CSS_SGI_PLATFORM_VARIANT), \
+ $(filter $(CSS_SGI_PLATFORM_VARIANT),$(RD_N2_VARIANTS)))
+ $(error "CSS_SGI_PLATFORM_VARIANT for RD-N2 should be 0 or 1, currently set \
+ to ${CSS_SGI_PLATFORM_VARIANT}.")
endif
diff --git a/plat/arm/rdinfra/rdn2/topology.c b/plat/arm/rdinfra/rdn2/topology.c
index ad13285..6918638 100644
--- a/plat/arm/rdinfra/rdn2/topology.c
+++ b/plat/arm/rdinfra/rdn2/topology.c
@@ -28,6 +28,7 @@
{ 6, 0 },
/* Cluster7: 1 core */
{ 7, 0 },
+#if (CSS_SGI_PLATFORM_VARIANT == 0)
/* Cluster8: 1 core */
{ 8, 0 },
/* Cluster9: 1 core */
@@ -44,6 +45,7 @@
{ 14, 0 },
/* Cluster15: 1 core */
{ 15, 0 },
+#endif
};
/*
@@ -71,6 +73,7 @@
CSS_SGI_MAX_CPUS_PER_CLUSTER,
/* Number of children for the 8th node */
CSS_SGI_MAX_CPUS_PER_CLUSTER,
+#if (CSS_SGI_PLATFORM_VARIANT == 0)
/* Number of children for the 9th node */
CSS_SGI_MAX_CPUS_PER_CLUSTER,
/* Number of children for the 10th node */
@@ -87,6 +90,7 @@
CSS_SGI_MAX_CPUS_PER_CLUSTER,
/* Number of children for the 16th node */
CSS_SGI_MAX_CPUS_PER_CLUSTER
+#endif
};
const unsigned char *tftf_plat_get_pwr_domain_tree_desc(void)