Merge "test(trp): test el3-rmm ide km interface"
diff --git a/docs/getting_started/requirements.rst b/docs/getting_started/requirements.rst
index d94e0cf..3c27b9d 100644
--- a/docs/getting_started/requirements.rst
+++ b/docs/getting_started/requirements.rst
@@ -40,7 +40,7 @@
Note that at least Python 3.8 is required.
Download and install the GNU cross-toolchain from Arm. The TF-A Tests have
-been tested with version 13.3.Rel1 (gcc 13.3):
+been tested with version 14.2.Rel1 (GCC 14.2):
- `GCC cross-toolchain`_
@@ -53,4 +53,4 @@
--------------
-*Copyright (c) 2019-2024, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2025, Arm Limited. All rights reserved.*
diff --git a/lib/power_management/suspend/aarch64/asm_tftf_suspend.S b/lib/power_management/suspend/aarch64/asm_tftf_suspend.S
index c643475..770a1bd 100644
--- a/lib/power_management/suspend/aarch64/asm_tftf_suspend.S
+++ b/lib/power_management/suspend/aarch64/asm_tftf_suspend.S
@@ -130,6 +130,9 @@
msr ttbr0_el2, x3
msr tcr_el2, x4
msr vbar_el2, x5
+
+ /* make sure whatever just got turned on is in effect */
+ isb
/*
* Check if the processor supports SME
*/
diff --git a/plat/arm/neoverse_rd/common/include/nrd1/nrd_css_def1.h b/plat/arm/neoverse_rd/common/include/nrd1/nrd_css_def1.h
deleted file mode 100644
index 2668c62..0000000
--- a/plat/arm/neoverse_rd/common/include/nrd1/nrd_css_def1.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * This file is limited to include the CSS specific memory and interrupt map
- * definitions for the first generation platforms based on the A75, N1 and V1
- * CPUs. There are minor differences in the memory map of these platforms and
- * those differences are not in the scope of this file.
- */
-
-#ifndef NRD_CSS_DEF1_H
-#define NRD_CSS_DEF1_H
-
-/*******************************************************************************
- * CSS memory map related defines
- ******************************************************************************/
-
-/* Sub-system Peripherals */
-#define NRD_CSS_PERIPH0_BASE UL(0x2A000000)
-#define NRD_CSS_PERIPH0_SIZE UL(0x26000000)
-
-/* Peripherals and PCIe expansion area */
-#define NRD_CSS_PERIPH1_BASE UL(0x60000000)
-#define NRD_CSS_PERIPH1_SIZE UL(0x20000000)
-
-/* DRAM base address and size */
-#define NRD_CSS_DRAM1_BASE UL(0x80000000)
-#define NRD_CSS_DRAM1_SIZE UL(0x80000000)
-
-/* AP Non-Secure UART related constants */
-#define NRD_CSS_NSEC_UART_BASE UL(0x2A400000)
-
-/* Base address of trusted watchdog */
-#define NRD_CSS_TWDOG_BASE UL(0x2A480000)
-
-/* Base address of non-trusted watchdog */
-#define NRD_CSS_WDOG_BASE UL(0x1C0F0000)
-
-/* Memory mapped Generic timer interfaces */
-#define NRD_CSS_NSEC_CNT_BASE1 UL(0x2A830000)
-
-#endif /* NRD_CSS_DEF1_H */
\ No newline at end of file
diff --git a/plat/arm/neoverse_rd/common/include/nrd1/nrd_css_fw_def1.h b/plat/arm/neoverse_rd/common/include/nrd1/nrd_css_fw_def1.h
deleted file mode 100644
index 55356e6..0000000
--- a/plat/arm/neoverse_rd/common/include/nrd1/nrd_css_fw_def1.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * This file is limited to include the CSS firmware specific definitions for
- * the first generation platforms based on the A75, N1 and V1 CPUs.
- */
-
-#ifndef NRD1_CSS_FW_DEF1_H
-#define NRD1_CSS_FW_DEF1_H
-
-#include "nrd_css_def1.h"
-
-/*******************************************************************************
- * Console config
- ******************************************************************************/
-
-#define NRD_CSS_NSEC_CLK_IN_HZ UL(7372800)
-
-#endif /* NRD_CSS_FW_DEF1_H */
\ No newline at end of file
diff --git a/plat/arm/neoverse_rd/common/include/nrd1/nrd_plat_arm_def1.h b/plat/arm/neoverse_rd/common/include/nrd1/nrd_plat_arm_def1.h
deleted file mode 100644
index 6a5085f..0000000
--- a/plat/arm/neoverse_rd/common/include/nrd1/nrd_plat_arm_def1.h
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * This file is limited to include the platform port definitions for the
- * first generation platforms based on the A75, N1 and V1 CPUs.
- */
-
-#ifndef NRD_PLAT_ARM_DEF1_H
-#define NRD_PLAT_ARM_DEF1_H
-
-#ifndef __ASSEMBLER__
-#include <lib/mmio.h>
-#endif /* __ASSEMBLER__ */
-
-#include <lib/utils_def.h>
-#include "nrd_css_fw_def1.h"
-#include "nrd_ros_def1.h"
-
-/*******************************************************************************
- * Linker related definitions
- ******************************************************************************/
-
-/* Platform binary types for linking */
-#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
-#define PLATFORM_LINKER_ARCH aarch64
-
-/*******************************************************************************
- * Stack size
- ******************************************************************************/
-
-/* Size of cacheable stacks */
-#define PLATFORM_STACK_SIZE U(0x1400) /* 5120 bytes */
-
-/* Size of coherent stacks */
-#define PCPU_DV_MEM_STACK_SIZE U(0x600) /* 1536 bytes */
-
-/*******************************************************************************
- * Core count
- ******************************************************************************/
-
-#define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \
- NRD_MAX_CPUS_PER_CLUSTER)
-#define PLATFORM_NUM_AFFS (PLAT_ARM_CLUSTER_COUNT + \
- PLATFORM_CORE_COUNT)
-
-/*******************************************************************************
- * Power related definitions
- ******************************************************************************/
-
-#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL1
-
-#define PLAT_MAX_PWR_LEVEL PLATFORM_MAX_AFFLVL
-#define PLAT_MAX_PWR_STATES_PER_LVL U(2)
-
-/* Local state bit width for each level in the state-ID field of power state */
-#define PLAT_LOCAL_PSTATE_WIDTH U(4)
-
-/*******************************************************************************
- * XLAT definitions
- ******************************************************************************/
-
-/* Platform specific page table and MMU setup constants */
-#define MAX_XLAT_TABLES U(6)
-#define MAX_MMAP_REGIONS U(16)
-
-/*******************************************************************************
- * I/O definitions
- ******************************************************************************/
-
-/* I/O Storage NOR flash device */
-#define MAX_IO_DEVICES U(1)
-#define MAX_IO_HANDLES U(1)
-
-/*******************************************************************************
- * Non-Secure Software Generated Interupts IDs
- ******************************************************************************/
-
-/* Non-Secure Software Generated Interupts IDs */
-#define IRQ_NS_SGI_0 U(0)
-#define IRQ_NS_SGI_7 U(7)
-
-/* Maximum SPI */
-#define PLAT_MAX_SPI_OFFSET_ID U(64)
-
-/*******************************************************************************
- * Timer related config
- ******************************************************************************/
-
-/* Per-CPU Hypervisor Timer Interrupt ID */
-#define IRQ_PCPU_HP_TIMER U(26)
-
-/* Memory mapped Generic timer interfaces */
-#define SYS_CNT_BASE1 NRD_CSS_NSEC_CNT_BASE1
-
-/* AP_REFCLK Generic Timer, Non-secure. */
-#define IRQ_CNTPSIRQ1 U(92)
-
-/* Times(in ms) used by test code for completion of different events */
-#define PLAT_SUSPEND_ENTRY_TIME U(15)
-#define PLAT_SUSPEND_ENTRY_EXIT_TIME U(30)
-
-/*******************************************************************************
- * Console config
- ******************************************************************************/
-
-#define PLAT_ARM_UART_BASE NRD_CSS_NSEC_UART_BASE
-#define PLAT_ARM_UART_CLK_IN_HZ NRD_CSS_NSEC_CLK_IN_HZ
-
-/*******************************************************************************
- * DRAM config
- ******************************************************************************/
-
-/* TF-A reserves DRAM space 0xFF000000- 0xFFFFFFFF for TZC */
-#define DRAM_BASE NRD_CSS_DRAM1_BASE
-#define DRAM_SIZE (NRD_CSS_DRAM1_SIZE - 0x1000000)
-
-/*******************************************************************************
- * Cache related config
- ******************************************************************************/
-
-#define CACHE_WRITEBACK_SHIFT U(6)
-#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
-
-/*******************************************************************************
- * Run-time address of the TFTF image.
- * It has to match the location where the Trusted Firmware-A loads the BL33
- * image.
- ******************************************************************************/
-
-#define TFTF_BASE UL(0xE0000000)
-
-/*******************************************************************************
- * TFTF NVM configs
- ******************************************************************************/
-
-#define TFTF_NVM_OFFSET U(0x0)
-#define TFTF_NVM_SIZE UL(0x08000000) /* 128 MB */
-
-/*******************************************************************************
- * Watchdog related config
- ******************************************************************************/
-
-/* Base address of trusted watchdog (SP805) */
-#define SP805_TWDOG_BASE NRD_CSS_TWDOG_BASE
-
-/* Base address of non-trusted watchdog (SP805) */
-#define SP805_WDOG_BASE NRD_CSS_WDOG_BASE
-
-/* Trusted watchdog (SP805) Interrupt ID */
-#define IRQ_TWDOG_INTID U(86)
-
-/*******************************************************************************
- * Flash related config
- ******************************************************************************/
-
-/* Base address and size of external NVM flash */
-#define FLASH_BASE NRD_ROS_FLASH_BASE
-#define FLASH_SIZE NRD_ROS_FLASH_SIZE
-#define NOR_FLASH_BLOCK_SIZE UL(0x40000) /* 256KB */
-
-#endif /* NRD_PLAT_ARM_DEF1_H */
\ No newline at end of file
diff --git a/plat/arm/neoverse_rd/common/include/nrd1/nrd_ros_def1.h b/plat/arm/neoverse_rd/common/include/nrd1/nrd_ros_def1.h
deleted file mode 100644
index 3c1764b..0000000
--- a/plat/arm/neoverse_rd/common/include/nrd1/nrd_ros_def1.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * This file is limited to include the RoS specific definitions for the first
- * generation platforms based on the A75, N1 and V1 CPUs. RoS (Rest Of System)
- * is used to refer to the part of the reference design platform that excludes
- * CSS.
- */
-
-#ifndef NRD_ROS_DEF1_H
-#define NRD_ROS_DEF1_H
-
-/*******************************************************************************
- * ROS configs
- ******************************************************************************/
-
-/* Base address and size of external NVM flash */
-#define NRD_ROS_FLASH_BASE UL(0x08000000) /* 128MB */
-#define NRD_ROS_FLASH_SIZE UL(0x04000000) /* 64MB */
-
-#endif /* NRD_ROS_DEF1_H */
\ No newline at end of file
diff --git a/plat/arm/neoverse_rd/platform/rdn1edge/include/platform_def.h b/plat/arm/neoverse_rd/platform/rdn1edge/include/platform_def.h
deleted file mode 100644
index 544e7b8..0000000
--- a/plat/arm/neoverse_rd/platform/rdn1edge/include/platform_def.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLATFORM_DEF_H
-#define PLATFORM_DEF_H
-
-#include <nrd1/nrd_plat_arm_def1.h>
-
-#define PLAT_ARM_CLUSTER_COUNT U(2)
-#define NRD_MAX_CPUS_PER_CLUSTER U(4)
-#define NRD_MAX_PE_PER_CPU U(1)
-
-/* GIC related constants */
-#define PLAT_ARM_GICD_BASE UL(0x30000000)
-#define PLAT_ARM_GICC_BASE UL(0x2C000000)
-#define PLAT_ARM_GICR_BASE UL(0x300C0000)
-
-/* Platform specific page table and MMU setup constants */
-#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
-#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
-
-#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/neoverse_rd/platform/rdn1edge/platform.mk b/plat/arm/neoverse_rd/platform/rdn1edge/platform.mk
deleted file mode 100644
index 9f92efd..0000000
--- a/plat/arm/neoverse_rd/platform/rdn1edge/platform.mk
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-include plat/arm/neoverse_rd/common/nrd_common.mk
-
-PLAT_INCLUDES += -Iplat/arm/neoverse_rd/platform/rdn1edge/include/
-
-PLAT_SOURCES += plat/arm/neoverse_rd/platform/rdn1edge/topology.c
-
-PLAT_TESTS_SKIP_LIST := plat/arm/neoverse_rd/platform/rdn1edge/tests_to_skip.txt
-
-ifdef NRD_PLATFORM_VARIANT
-$(error "NRD_PLATFORM_VARIANT should not be set for RD-N1-Edge, \
- currently set to ${NRD_PLATFORM_VARIANT}.")
-endif
diff --git a/plat/arm/neoverse_rd/platform/rdn1edge/tests_to_skip.txt b/plat/arm/neoverse_rd/platform/rdn1edge/tests_to_skip.txt
deleted file mode 100644
index 6341809..0000000
--- a/plat/arm/neoverse_rd/platform/rdn1edge/tests_to_skip.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-# OS-initiated mode is not supported on RD-N1Edge
-PSCI CPU Suspend in OSI mode
-
-# System suspend is not supported as there are no wakeup sources in RD-N1Edge FVP
-PSCI STAT/Stats test cases after system suspend
-PSCI System Suspend Validation
diff --git a/plat/arm/neoverse_rd/platform/rdn1edge/topology.c b/plat/arm/neoverse_rd/platform/rdn1edge/topology.c
deleted file mode 100644
index cb79ba6..0000000
--- a/plat/arm/neoverse_rd/platform/rdn1edge/topology.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-#include <plat_topology.h>
-#include <tftf_lib.h>
-
-static const struct {
- unsigned int cluster_id;
- unsigned int cpu_id;
-} plat_cores[] = {
- /* Cluster0: 4 cores*/
- { 0, 0 },
- { 0, 1 },
- { 0, 2 },
- { 0, 3 },
- /* Cluster1: 4 cores */
- { 1, 0 },
- { 1, 1 },
- { 1, 2 },
- { 1, 3 },
-};
-
-/*
- * The power domain tree descriptor. The cluster power domains are
- * arranged so that when the PSCI generic code creates the power domain tree,
- * the indices of the CPU power domain nodes it allocates match the linear
- * indices returned by plat_core_pos_by_mpidr().
- */
-const unsigned char plat_pd_tree_desc[] = {
- /* Number of root nodes */
- PLAT_ARM_CLUSTER_COUNT,
- /* Number of children for the 1st node */
- NRD_MAX_CPUS_PER_CLUSTER,
- /* Number of children for the 2nd node */
- NRD_MAX_CPUS_PER_CLUSTER
-};
-
-const unsigned char *tftf_plat_get_pwr_domain_tree_desc(void)
-{
- return plat_pd_tree_desc;
-}
-
-uint64_t tftf_plat_get_mpidr(unsigned int core_pos)
-{
- unsigned int mpid;
-
- assert(core_pos < PLATFORM_CORE_COUNT);
-
- mpid = make_mpid(
- plat_cores[core_pos].cluster_id,
- plat_cores[core_pos].cpu_id);
-
- return mpid;
-}
diff --git a/plat/arm/neoverse_rd/platform/rdv1/include/platform_def.h b/plat/arm/neoverse_rd/platform/rdv1/include/platform_def.h
deleted file mode 100644
index de94ac9..0000000
--- a/plat/arm/neoverse_rd/platform/rdv1/include/platform_def.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLATFORM_DEF_H
-#define PLATFORM_DEF_H
-
-#include <nrd1/nrd_plat_arm_def1.h>
-
-#define PLAT_ARM_CLUSTER_COUNT U(16)
-#define NRD_MAX_CPUS_PER_CLUSTER U(1)
-#define NRD_MAX_PE_PER_CPU U(1)
-
-/* GIC related constants */
-#define PLAT_ARM_GICD_BASE UL(0x30000000)
-#define PLAT_ARM_GICR_BASE UL(0x30140000)
-#define PLAT_ARM_GICC_BASE UL(0x2C000000)
-
-/* Platform specific page table and MMU setup constants */
-#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 42)
-#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 42)
-
-#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/neoverse_rd/platform/rdv1/platform.mk b/plat/arm/neoverse_rd/platform/rdv1/platform.mk
deleted file mode 100644
index cfb8543..0000000
--- a/plat/arm/neoverse_rd/platform/rdv1/platform.mk
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-include plat/arm/neoverse_rd/common/nrd_common.mk
-
-PLAT_INCLUDES += -Iplat/arm/neoverse_rd/platform/rdv1/include/
-
-PLAT_SOURCES += plat/arm/neoverse_rd/platform/rdv1/topology.c
-
-PLAT_TESTS_SKIP_LIST := plat/arm/neoverse_rd/platform/rdv1/tests_to_skip.txt
-
-ifdef NRD_PLATFORM_VARIANT
-$(error "NRD_PLATFORM_VARIANT should not be set for RD-V1, \
- currently set to ${NRD_PLATFORM_VARIANT}.")
-endif
diff --git a/plat/arm/neoverse_rd/platform/rdv1/tests_to_skip.txt b/plat/arm/neoverse_rd/platform/rdv1/tests_to_skip.txt
deleted file mode 100644
index d62b9dd..0000000
--- a/plat/arm/neoverse_rd/platform/rdv1/tests_to_skip.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-#
-# Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-# OS-initiated mode is not supported on RD-V1
-PSCI CPU Suspend in OSI mode
-
-# System suspend is not supported as there are no wakeup sources in RD-V1 FVP
-PSCI STAT/Stats test cases after system suspend
-PSCI System Suspend Validation
-
-# The following tests hang during the test execution
-Timer framework Validation/Stress test the timer framework
-PSCI Affinity Info/Affinity info level0 powerdown
-PSCI CPU Suspend/CPU suspend to powerdown at level 0
-PSCI CPU Suspend/CPU suspend to powerdown at level 1
-
-# The following tests are not supported on RD-V1
-CPU extensions/Use trace buffer control Registers
-CPU extensions/Use trace filter control Registers
diff --git a/plat/arm/neoverse_rd/platform/rdv1/topology.c b/plat/arm/neoverse_rd/platform/rdv1/topology.c
deleted file mode 100644
index 882bffb..0000000
--- a/plat/arm/neoverse_rd/platform/rdv1/topology.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-#include <plat_topology.h>
-#include <tftf_lib.h>
-
-static const struct {
- unsigned int cluster_id;
- unsigned int cpu_id;
-} plat_cores[] = {
- /* Cluster0: 1 core */
- { 0, 0 },
- /* Cluster1: 1 core */
- { 1, 0 },
- /* Cluster2: 1 core */
- { 2, 0 },
- /* Cluster3: 1 core */
- { 3, 0 },
- /* Cluster4: 1 core */
- { 4, 0 },
- /* Cluster5: 1 core */
- { 5, 0 },
- /* Cluster6: 1 core */
- { 6, 0 },
- /* Cluster7: 1 core */
- { 7, 0 },
- /* Cluster8: 1 core */
- { 8, 0 },
- /* Cluster9: 1 core */
- { 9, 0 },
- /* Cluster10: 1 core */
- { 10, 0 },
- /* Cluster11: 1 core */
- { 11, 0 },
- /* Cluster12: 1 core */
- { 12, 0 },
- /* Cluster13: 1 core */
- { 13, 0 },
- /* Cluster14: 1 core */
- { 14, 0 },
- /* Cluster15: 1 core */
- { 15, 0 },
-};
-
-/*
- * The power domain tree descriptor. The cluster power domains are
- * arranged so that when the PSCI generic code creates the power domain tree,
- * the indices of the CPU power domain nodes it allocates match the linear
- * indices returned by plat_core_pos_by_mpidr().
- */
-const unsigned char plat_pd_tree_desc[] = {
- /* Number of root nodes */
- PLAT_ARM_CLUSTER_COUNT,
- /* Number of children for the 1st node */
- NRD_MAX_CPUS_PER_CLUSTER,
- /* Number of children for the 2nd node */
- NRD_MAX_CPUS_PER_CLUSTER,
- /* Number of children for the 3rd node */
- NRD_MAX_CPUS_PER_CLUSTER,
- /* Number of children for the 4th node */
- NRD_MAX_CPUS_PER_CLUSTER,
- /* Number of children for the 5th node */
- NRD_MAX_CPUS_PER_CLUSTER,
- /* Number of children for the 6th node */
- NRD_MAX_CPUS_PER_CLUSTER,
- /* Number of children for the 7th node */
- NRD_MAX_CPUS_PER_CLUSTER,
- /* Number of children for the 8th node */
- NRD_MAX_CPUS_PER_CLUSTER,
- /* Number of children for the 9th node */
- NRD_MAX_CPUS_PER_CLUSTER,
- /* Number of children for the 10th node */
- NRD_MAX_CPUS_PER_CLUSTER,
- /* Number of children for the 11th node */
- NRD_MAX_CPUS_PER_CLUSTER,
- /* Number of children for the 12th node */
- NRD_MAX_CPUS_PER_CLUSTER,
- /* Number of children for the 13th node */
- NRD_MAX_CPUS_PER_CLUSTER,
- /* Number of children for the 14th node */
- NRD_MAX_CPUS_PER_CLUSTER,
- /* Number of children for the 15th node */
- NRD_MAX_CPUS_PER_CLUSTER,
- /* Number of children for the 16th node */
- NRD_MAX_CPUS_PER_CLUSTER
-};
-
-const unsigned char *tftf_plat_get_pwr_domain_tree_desc(void)
-{
- return plat_pd_tree_desc;
-}
-
-uint64_t tftf_plat_get_mpidr(unsigned int core_pos)
-{
- unsigned int mpid;
-
- assert(core_pos < PLATFORM_CORE_COUNT);
-
- mpid = make_mpid(plat_cores[core_pos].cluster_id,
- plat_cores[core_pos].cpu_id);
-
- return (uint64_t)mpid;
-}
diff --git a/plat/arm/neoverse_rd/platform/sgi575/include/platform_def.h b/plat/arm/neoverse_rd/platform/sgi575/include/platform_def.h
deleted file mode 100644
index e8a4606..0000000
--- a/plat/arm/neoverse_rd/platform/sgi575/include/platform_def.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLATFORM_DEF_H
-#define PLATFORM_DEF_H
-
-#include <nrd1/nrd_plat_arm_def1.h>
-
-#define PLAT_ARM_CLUSTER_COUNT U(2)
-#define NRD_MAX_CPUS_PER_CLUSTER U(4)
-#define NRD_MAX_PE_PER_CPU U(1)
-
-/* GIC related constants */
-#define PLAT_ARM_GICD_BASE UL(0x30000000)
-#define PLAT_ARM_GICC_BASE UL(0x2C000000)
-#define PLAT_ARM_GICR_BASE UL(0x300C0000)
-
-/* Platform specific page table and MMU setup constants */
-#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
-#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
-
-#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/neoverse_rd/platform/sgi575/platform.mk b/plat/arm/neoverse_rd/platform/sgi575/platform.mk
deleted file mode 100644
index 5e81be5..0000000
--- a/plat/arm/neoverse_rd/platform/sgi575/platform.mk
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-include plat/arm/neoverse_rd/common/nrd_common.mk
-
-PLAT_INCLUDES += -Iplat/arm/neoverse_rd/platform/sgi575/include/
-
-PLAT_SOURCES += plat/arm/neoverse_rd/platform/sgi575/sgi575_topology.c
-
-PLAT_TESTS_SKIP_LIST := plat/arm/neoverse_rd/platform/sgi575/tests_to_skip.txt
-
-ifdef NRD_PLATFORM_VARIANT
-$(error "NRD_PLATFORM_VARIANT should not be set for SGI-575, \
- currently set to ${NRD_PLATFORM_VARIANT}.")
-endif
diff --git a/plat/arm/neoverse_rd/platform/sgi575/sgi575_topology.c b/plat/arm/neoverse_rd/platform/sgi575/sgi575_topology.c
deleted file mode 100644
index f38c197..0000000
--- a/plat/arm/neoverse_rd/platform/sgi575/sgi575_topology.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-#include <plat_topology.h>
-#include <tftf_lib.h>
-
-static const struct {
- unsigned int cluster_id;
- unsigned int cpu_id;
-} sgi575_cores[] = {
- /* Cluster0: 4 cores*/
- { 0, 0 },
- { 0, 1 },
- { 0, 2 },
- { 0, 3 },
- /* Cluster1: 4 cores */
- { 1, 0 },
- { 1, 1 },
- { 1, 2 },
- { 1, 3 },
-};
-
-/*
- * The power domain tree descriptor. The cluster power domains are
- * arranged so that when the PSCI generic code creates the power domain tree,
- * the indices of the CPU power domain nodes it allocates match the linear
- * indices returned by plat_core_pos_by_mpidr().
- */
-const unsigned char sgi575_pd_tree_desc[] = {
- /* Number of root nodes */
- PLAT_ARM_CLUSTER_COUNT,
- /* Number of children for the 1st node */
- NRD_MAX_CPUS_PER_CLUSTER,
- /* Number of children for the 2nd node */
- NRD_MAX_CPUS_PER_CLUSTER
-};
-
-const unsigned char *tftf_plat_get_pwr_domain_tree_desc(void)
-{
- return sgi575_pd_tree_desc;
-}
-
-uint64_t tftf_plat_get_mpidr(unsigned int core_pos)
-{
- unsigned int mpid;
-
- assert(core_pos < PLATFORM_CORE_COUNT);
-
- mpid = make_mpid(
- sgi575_cores[core_pos].cluster_id,
- sgi575_cores[core_pos].cpu_id);
-
- return mpid;
-}
diff --git a/plat/arm/neoverse_rd/platform/sgi575/tests_to_skip.txt b/plat/arm/neoverse_rd/platform/sgi575/tests_to_skip.txt
deleted file mode 100644
index 8817946..0000000
--- a/plat/arm/neoverse_rd/platform/sgi575/tests_to_skip.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-# OS-initiated mode is not supported on SGI-575
-PSCI CPU Suspend in OSI mode
-
-# System suspend is not supported as there are no wakeup sources in SGI-575 FVP
-PSCI STAT/Stats test cases after system suspend
-PSCI System Suspend Validation
diff --git a/tftf/framework/aarch32/entrypoint.S b/tftf/framework/aarch32/entrypoint.S
index eaa0788..3e40ab9 100644
--- a/tftf/framework/aarch32/entrypoint.S
+++ b/tftf/framework/aarch32/entrypoint.S
@@ -16,6 +16,12 @@
* ----------------------------------------------------------------------------
*/
func tftf_entrypoint
+#if TRANSFER_LIST
+ mov r4, r0
+ mov r5, r1
+ mov r6, r2
+ mov r7, r3
+#endif
bl arch_init
/* --------------------------------------------------------------------
@@ -53,6 +59,19 @@
bl zeromem
/* --------------------------------------------------------------------
+ * Save transfer list and hw_config addresses passed in registers r0 to
+ * r3 from the previous bootloader.
+ * --------------------------------------------------------------------
+ */
+#if TRANSFER_LIST
+ mov r0, r4
+ mov r1, r5
+ mov r2, r6
+ mov r3, r7
+ bl save_handoff_params
+#endif
+
+ /* --------------------------------------------------------------------
* Give ourselves a small coherent stack to ease the pain of
* initializing the MMU
* --------------------------------------------------------------------
@@ -172,3 +191,18 @@
/* Primary core MPID already saved */
b panic
endfunc save_primary_mpid
+
+/* ----------------------------------------------------------------------------
+ * Save transfer list and hw_config addresses passed in registers r0 to r3 from
+ * the previous bootloader.
+ * ----------------------------------------------------------------------------
+ */
+func save_handoff_params
+ ldr r4, =ns_tl
+ str r3, [r4]
+ ldr r4, =tl_signature
+ str r1, [r4]
+ ldr r4, =hw_config_base
+ str r2, [r4]
+ bx lr
+endfunc save_handoff_params
diff --git a/tftf/tests/misc_tests/test_firmware_handoff.c b/tftf/tests/misc_tests/test_firmware_handoff.c
index 00cebd3..61091ae 100644
--- a/tftf/tests/misc_tests/test_firmware_handoff.c
+++ b/tftf/tests/misc_tests/test_firmware_handoff.c
@@ -20,8 +20,15 @@
{
struct transfer_list_header *tl = (struct transfer_list_header *)ns_tl;
- assert(tl_signature ==
- TRANSFER_LIST_HANDOFF_X1_VALUE(TRANSFER_LIST_VERSION));
+#if __aarch64__
+ uint64_t signature = TRANSFER_LIST_HANDOFF_X1_VALUE(TRANSFER_LIST_VERSION);
+#else
+ uint32_t signature = TRANSFER_LIST_HANDOFF_R1_VALUE(TRANSFER_LIST_VERSION);
+#endif /* __aarch64__ */
+
+ if (signature != tl_signature) {
+ return TEST_RESULT_FAIL;
+ }
if (transfer_list_check_header(tl) == TL_OPS_NON) {
return TEST_RESULT_FAIL;