feat(versal-net): introduce platform support
Introduce platform support for AMD-Xilinx Versal NET, an adaptive
compute acceleration platform (ACAP). The Versal NET is designed to
offer a wide range of compute, acceleration, and connectivity
options, including high-speed networking interfaces.
- pl011 is used for console.
- TTC is used for Timers.
- NVM is not supported.
For Versal devices with 1 cluster and 2 cores, the SCNTR and SCNTRS
registers are not accessible from NS EL1, so we are using TTC timers
instead.
For Versal NET devices with 4 clusters and 4 cores per cluster, the
SCNTR and SCNTRS registers are not accessible from NS EL1, so we
are using TTC timers instead.
summary:
=================================
Tests Skipped : 128
Tests Passed : 34
Tests Failed : 7
Tests Crashed : 0
Total tests : 169
=================================
NOTICE: Exiting tests.
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I80e76d9f898f5ebca91a403ff802857ea70d7868
diff --git a/plat/xilinx/versal_net/aarch64/plat_helpers.S b/plat/xilinx/versal_net/aarch64/plat_helpers.S
new file mode 100644
index 0000000..77012ef
--- /dev/null
+++ b/plat/xilinx/versal_net/aarch64/plat_helpers.S
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <platform_def.h>
+
+ .global platform_get_core_pos
+ .global plat_crash_console_init
+ .global plat_crash_console_flush
+ .global plat_crash_console_putc
+
+/*----------------------------------------------------------------------
+ * unsigned int platform_get_core_pos(u_register_t mpid)
+ *
+ * Function to calculate the core position.
+ *
+ * clobbers: x0 - x3
+ * ---------------------------------------------------------------------
+ */
+func platform_get_core_pos
+ /* x1 = core-id inside cluster */
+ ubfx x1, x0, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
+ /* x2 = cluster-id */
+ ubfx x2, x0, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
+
+ /* core-position = cluster-id * cores per cluster + core-id */
+ mov x3, #PLATFORM_CORE_COUNT_PER_CLUSTER
+ madd x0, x2, x3, x1
+ ret
+endfunc platform_get_core_pos
+
+ /* ---------------------------------------------
+ * int plat_crash_console_init(void)
+ * Function to initialize the crash console
+ * without a C Runtime to print crash report.
+ * Clobber list : x0 - x4
+ * ---------------------------------------------
+ */
+func plat_crash_console_init
+ mov_imm x0, CRASH_CONSOLE_BASE
+ mov_imm x1, PL011_UART_CLK_IN_HZ
+ mov_imm x2, PL011_BAUDRATE
+ b console_core_init
+endfunc plat_crash_console_init
+
+ /* ---------------------------------------------
+ * int plat_crash_console_putc(int c)
+ * Function to print a character on the crash
+ * console without a C Runtime.
+ * Clobber list : x1, x2
+ * ---------------------------------------------
+ */
+func plat_crash_console_putc
+ mov_imm x1, CRASH_CONSOLE_BASE
+ b console_core_putc
+endfunc plat_crash_console_putc
+
+ /* ---------------------------------------------
+ * int plat_crash_console_flush()
+ * Function to force a write of all buffered
+ * data that hasn't been output.
+ * Out : return -1 on error else return 0.
+ * Clobber list : r0 - r1
+ * ---------------------------------------------
+ */
+func plat_crash_console_flush
+ mov_imm x1, CRASH_CONSOLE_BASE
+ b console_core_flush
+endfunc plat_crash_console_flush
diff --git a/plat/xilinx/versal_net/include/platform_def.h b/plat/xilinx/versal_net/include/platform_def.h
new file mode 100644
index 0000000..b55d337
--- /dev/null
+++ b/plat/xilinx/versal_net/include/platform_def.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <arch.h>
+
+#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
+#define PLATFORM_LINKER_ARCH aarch64
+
+#define TFTF_BASE U(0x8000000)
+
+#define CACHE_WRITEBACK_GRANULE U(0x40)
+
+#define PLATFORM_CLUSTER_COUNT U(4)
+#define PLATFORM_CORE_COUNT_PER_CLUSTER U(4)
+#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
+ PLATFORM_CORE_COUNT_PER_CLUSTER)
+#define PLATFORM_NUM_AFFS (PLATFORM_CORE_COUNT + \
+ PLATFORM_CLUSTER_COUNT + 1)
+#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2
+#define PLAT_MAX_PWR_LEVEL MPIDR_AFFLVL2
+#define PLAT_MAX_PWR_STATES_PER_LVL U(2)
+
+
+#define PLATFORM_STACK_SIZE U(0x440)
+#define PCPU_DV_MEM_STACK_SIZE U(0x440)
+
+
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
+#define MAX_XLAT_TABLES U(8)
+#define MAX_MMAP_REGIONS U(16)
+
+#define DRAM_BASE U(0x0)
+#define DRAM_SIZE U(0x80000000)
+
+/*
+ * TFTF_NVM_OFFSET/SIZE correspond to the NVM partition in the partition
+ * table
+ */
+#define TFTF_NVM_SIZE U(0x600000)
+#define TFTF_NVM_OFFSET U(0x20000000)
+
+/* Local state bit width for each level in the state-ID field of power state */
+#define PLAT_LOCAL_PSTATE_WIDTH U(4)
+
+/* GIC related addresses from datasheet */
+#define GICD_REG_BASE U(0xe2000000)
+#define GICR_REG_BASE U(0xe2060000)
+
+/* GICv3 is used, dummy definition to resolve build failure */
+#define GICC_REG_BASE U(0xe2000000)
+
+/*
+ * Memory mapped devices that we must create MMU mappings for them
+ */
+#define GIC_BASE GICD_REG_BASE
+#define GIC_SIZE U(0x01000000)
+
+#define TTC_BASE U(0xF1DC0000)
+#define TTC_SIZE U(0x00010000)
+
+#define SYS_CNT_BASE1 TTC_BASE
+#define SYS_CNT_SIZE TTC_SIZE
+
+#define LPD_IOU_SLCR U(0xF19A0000)
+#define LPD_IOU_SLCR_SIZE U(0x00010000)
+
+/* ARM PL011 UART */
+#define PL011_UART0_BASE U(0xf1920000)
+#define PL011_BAUDRATE U(115200)
+#define PL011_UART_CLK_IN_HZ U(100000000)
+
+#define PLAT_ARM_UART_BASE PL011_UART0_BASE
+#define PLAT_ARM_UART_SIZE U(0x1000)
+
+#define CRASH_CONSOLE_BASE PL011_UART0_BASE
+#define CRASH_CONSOLE_SIZE PLAT_ARM_UART_SIZE
+
+/*******************************************************************************
+ * Non-Secure Software Generated Interrupts IDs
+ ******************************************************************************/
+#define IRQ_NS_SGI_0 0
+#define IRQ_NS_SGI_1 1
+#define IRQ_NS_SGI_2 2
+#define IRQ_NS_SGI_3 3
+#define IRQ_NS_SGI_4 4
+#define IRQ_NS_SGI_5 5
+#define IRQ_NS_SGI_6 6
+#define IRQ_NS_SGI_7 7
+
+/* Per-CPU Hypervisor Timer Interrupt ID */
+#define IRQ_PCPU_HP_TIMER U(29)
+/* Datasheet: TIME00 event*/
+#define IRQ_CNTPSIRQ1 U(29)
+
+/* Refer to AM011(v1.5), Chapter 50, Page 430 */
+#define PLAT_MAX_SPI_OFFSET_ID U(223)
+
+/*
+ * Times(in ms) used by test code for completion of different events.
+ */
+#define PLAT_SUSPEND_ENTRY_TIME U(15)
+#define PLAT_SUSPEND_ENTRY_EXIT_TIME U(30)
+
+/*
+ * Dummy definitions that we need just to compile...
+ */
+#define ARM_SECURE_SERVICE_BUFFER_BASE U(0)
+#define ARM_SECURE_SERVICE_BUFFER_SIZE U(100)
+
+/* LPD_SWDT_INT, AM011(v1.5), Chapter 50, Page 428 */
+#define IRQ_TWDOG_INTID U(0x51)
+
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/xilinx/versal_net/include/util.h b/plat/xilinx/versal_net/include/util.h
new file mode 100644
index 0000000..840c14f
--- /dev/null
+++ b/plat/xilinx/versal_net/include/util.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef UTIL_H
+#define UTIL_H
+
+#include <platform_def.h>
+
+#define CPU_DEF(cluster, cpu) { cluster, cpu }
+
+#if (PLATFORM_CORE_COUNT_PER_CLUSTER == 1U)
+#define CLUSTER_DEF(cluster) \
+ CPU_DEF(cluster, 0)
+#elif (PLATFORM_CORE_COUNT_PER_CLUSTER == 2U)
+#define CLUSTER_DEF(cluster) \
+ CPU_DEF(cluster, 0), \
+ CPU_DEF(cluster, 1)
+#elif (PLATFORM_CORE_COUNT_PER_CLUSTER == 4U)
+#define CLUSTER_DEF(cluster) \
+ CPU_DEF(cluster, 0), \
+ CPU_DEF(cluster, 1), \
+ CPU_DEF(cluster, 2), \
+ CPU_DEF(cluster, 3)
+#endif
+
+#endif /* UTIL_H */
diff --git a/plat/xilinx/versal_net/platform.mk b/plat/xilinx/versal_net/platform.mk
new file mode 100644
index 0000000..398d12e
--- /dev/null
+++ b/plat/xilinx/versal_net/platform.mk
@@ -0,0 +1,27 @@
+#
+# Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+VERSAL_NET_PATH := plat/xilinx/versal_net
+
+PLAT_INCLUDES := -I${VERSAL_NET_PATH}/include/
+
+PLAT_SOURCES := drivers/arm/gic/arm_gic_v2v3.c \
+ drivers/arm/gic/gic_common.c \
+ drivers/arm/gic/gic_v2.c \
+ drivers/arm/gic/gic_v3.c \
+ drivers/arm/pl011/${ARCH}/pl011_console.S \
+ drivers/arm/timer/private_timer.c \
+ drivers/console/console.c \
+ ${VERSAL_NET_PATH}/versal_net_setup.c \
+ ${VERSAL_NET_PATH}/versal_net_pwr_state.c \
+ ${VERSAL_NET_PATH}/aarch64/plat_helpers.S \
+ ${VERSAL_NET_PATH}/timers.c
+
+PLAT_TESTS_SKIP_LIST := ${VERSAL_NET_PATH}/tests_to_skip.txt
+
+ifeq ($(USE_NVM),1)
+$(error "Versal NET port of TFTF doesn't currently support USE_NVM=1")
+endif
diff --git a/plat/xilinx/versal_net/tests_to_skip.txt b/plat/xilinx/versal_net/tests_to_skip.txt
new file mode 100644
index 0000000..95f6c1e
--- /dev/null
+++ b/plat/xilinx/versal_net/tests_to_skip.txt
@@ -0,0 +1,63 @@
+#
+# Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#
+################################################################################
+# Disable the listed tests for Versal NET Platform.
+################################################################################
+
+#TESTS: tftf-validation
+Framework Validation/Events API
+Framework Validation/NVM serialisation
+
+#TESTS: Timer framework Validation
+Timer framework Validation
+
+#TESTS: Boot requirement tests
+Boot requirement tests
+
+#TESTS: CPU Hotplug
+CPU Hotplug/CPU hotplug
+CPU Hotplug/CPU already on
+CPU Hotplug/Context ID passing
+CPU Hotplug/Invalid entry point
+
+#TESTS: PSCI System Suspend Validation
+PSCI System Suspend Validation/System suspend with cores on
+PSCI System Suspend Validation/Suspend system with cores in suspend
+
+#TESTS: CPU extensions
+CPU extensions/PMUv3 SMC counter preservation
+
+#TESTS: Performance tests
+Performance tests/Test cluster power up latency
+
+#TESTS: FF-A
+FF-A Setup and Discovery/FF-A RXTX unmap SP rxtx buffer
+FF-A Setup and Discovery/Test FFA_PARTITION_INFO_GET v1.0
+FF-A Memory Sharing/Lend memory, clear flag set
+SIMD,SVE Registers context/Check that SIMD registers context is preserved
+FF-A Interrupt
+FF-A Notifications
+
+#TESTS: AMD-Xilinx tests
+AMD-Xilinx tests
+
+#TESTS: psci
+PSCI Affinity Info/Affinity info level0 powerdown
+PSCI CPU Suspend/CPU suspend to powerdown at level 0
+PSCI CPU Suspend/CPU suspend to powerdown at level 1
+PSCI CPU Suspend/CPU suspend to powerdown at level 2
+PSCI CPU Suspend/CPU suspend to standby at level 0
+PSCI CPU Suspend/CPU suspend to standby at level 1
+PSCI CPU Suspend/CPU suspend to standby at level 2
+PSCI CPU Suspend in OSI mode/CPU suspend to powerdown at level 0 in OSI mode
+PSCI CPU Suspend in OSI mode/CPU suspend to powerdown at level 1 in OSI mode
+PSCI System Suspend Validation/System suspend multiple times
+PSCI System Suspend Validation/system suspend from all cores
+PSCI System Suspend Validation/Validate suspend to RAM functionality
+
+#TESTS: el3-power-state
+EL3 power state parser validation
diff --git a/plat/xilinx/versal_net/timers.c b/plat/xilinx/versal_net/timers.c
new file mode 100644
index 0000000..ce87b0f
--- /dev/null
+++ b/plat/xilinx/versal_net/timers.c
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <stddef.h>
+
+#include <debug.h>
+#include <mmio.h>
+#include <platform.h>
+#include <tftf_lib.h>
+#include <timer.h>
+#include <utils_def.h>
+
+#define TTC_OFFSET_TMR_0 U(0)
+#define TTC_OFFSET_TMR_1 U(4)
+#define TTC_OFFSET_TMR_2 U(8)
+
+#define TTC_CLK_CNTRL_OFFSET U(0x00) /* Clock Control Reg, RW */
+#define TTC_CNT_CNTRL_OFFSET U(0x0C) /* Counter Control Reg, RW */
+#define TTC_COUNT_VAL_OFFSET U(0x18) /* Counter Value Reg, RO */
+#define TTC_INTR_VAL_OFFSET U(0x24) /* Interval Count Reg, RW */
+#define TTC_ISR_OFFSET U(0x54) /* Interrupt Status Reg, RO */
+#define TTC_IER_OFFSET U(0x60) /* Interrupt Enable Reg, RW */
+
+#define TTC_CNT_CNTRL_DISABLE_MASK BIT(0)
+
+#define TTC_CLK_SEL_OFFSET U(0x360)
+#define TTC_CLK_SEL_MASK GENMASK(1, 0)
+
+#define TTC_CLK_SEL_PS_REF BIT(0)
+#define TTC_CLK_SEL_RPU_REF BIT(4)
+
+#define TIMER_IRQ U(75)
+
+#define RET_SUCCESS U(0)
+
+/*
+ * Setup the timers to use pre-scaling, using a fixed value for now that will
+ * work across most input frequency, but it may need to be more dynamic
+ */
+#define PRESCALE_EXPONENT U(16) /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
+#define PRESCALE U(65536) /* The exponent must match this */
+#define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1U)
+#define CLK_CNTRL_PRESCALE_EN BIT(0)
+#define CNT_CNTRL_RESET BIT(4)
+
+/* Resolution obtained as per the input clock and Prescale value
+ * Clock Selected : PS_REF_CLK
+ * Clock Value : 33333333Hz (33.33MHz)
+ * Prescalar for TTC, N : 15 (highest)
+ * Prescalar Applied 2^(N+1) : 65536
+ * Input clock : (PS_REF_CLK)/Prescalar) : 508.6263Hz
+ * Resolution (1/InputClock) : 1.966miliseconds ~2ms
+ */
+const unsigned long INTERVAL = 2;
+
+static void timer_write_32(uint32_t offset, uint32_t val)
+{
+ /* actual write */
+ mmio_write_32(SYS_CNT_BASE1 + offset, val);
+}
+
+static uint32_t timer_read_32(uint32_t offset)
+{
+ /* actual read */
+ return mmio_read_32(SYS_CNT_BASE1 + offset);
+}
+
+static int cancel_timer(void)
+{
+ /* Disable Interrupt */
+ timer_write_32(TTC_IER_OFFSET, 0);
+
+ /* Disable Counter */
+ timer_write_32(TTC_CLK_CNTRL_OFFSET, !CLK_CNTRL_PRESCALE_EN);
+ timer_write_32(TTC_CNT_CNTRL_OFFSET, !CLK_CNTRL_PRESCALE_EN);
+
+ return RET_SUCCESS;
+}
+
+static void clocksetup(void)
+{
+ timer_write_32(TTC_OFFSET_TMR_0 + TTC_CLK_CNTRL_OFFSET, 0x0);
+
+ mmio_write_32(LPD_IOU_SLCR + TTC_CLK_SEL_OFFSET, TTC_CLK_SEL_PS_REF);
+
+ VERBOSE("%s TTC_CLK_SEL = 0x%x\n", __func__,
+ mmio_read_32(LPD_IOU_SLCR + TTC_CLK_SEL_OFFSET));
+}
+
+static void setcounts(unsigned long time_out_ms)
+{
+ unsigned long intrvl = (time_out_ms / INTERVAL) + (time_out_ms % INTERVAL);
+
+ timer_write_32(TTC_INTR_VAL_OFFSET, intrvl);
+}
+
+static int program_timer(unsigned long time_out_ms)
+{
+ uint32_t reg;
+
+ /* Disable and program the counter */
+ reg = timer_read_32(TTC_CNT_CNTRL_OFFSET);
+ reg |= TTC_CNT_CNTRL_DISABLE_MASK;
+ timer_write_32(TTC_CNT_CNTRL_OFFSET, reg);
+
+ setcounts(time_out_ms);
+
+ /* Enable the interrupt */
+ timer_write_32(TTC_IER_OFFSET, 0x01);
+
+ /* Enable the counter */
+ reg |= CNT_CNTRL_RESET;
+ reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
+ timer_write_32(TTC_CNT_CNTRL_OFFSET, reg);
+
+ return RET_SUCCESS;
+}
+
+static int handler_timer(void)
+{
+ uint32_t status;
+
+ /* Disable the interrupts */
+ timer_write_32(TTC_IER_OFFSET, 0x00);
+
+ status = timer_read_32(TTC_ISR_OFFSET);
+ if (status & 0x1)
+ INFO("Timer Event! %x\n", status);
+ else
+ ERROR("Its not a Timer Event %d\n", status);
+
+ return RET_SUCCESS;
+}
+
+static const plat_timer_t versal_timers = {
+ .program = program_timer,
+ .cancel = cancel_timer,
+ .handler = handler_timer,
+ .timer_step_value = INTERVAL,
+ .timer_irq = TIMER_IRQ
+};
+
+int plat_initialise_timer_ops(const plat_timer_t **timer_ops)
+{
+ assert(timer_ops != NULL);
+
+ /* Disable all Interrupts on the TTC */
+ timer_write_32(TTC_OFFSET_TMR_0 + TTC_IER_OFFSET, 0);
+ timer_write_32(TTC_OFFSET_TMR_1 + TTC_IER_OFFSET, 0);
+ timer_write_32(TTC_OFFSET_TMR_2 + TTC_IER_OFFSET, 0);
+
+ clocksetup();
+
+ /*
+ * Setup the clock event timer to be an interval timer which
+ * is prescaled by 32 using the interval interrupt. Leave it
+ * disabled for now.
+ */
+ timer_write_32(TTC_OFFSET_TMR_0 + TTC_CNT_CNTRL_OFFSET, 0x23);
+ timer_write_32(TTC_OFFSET_TMR_0 + TTC_CLK_CNTRL_OFFSET,
+ CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN);
+ timer_write_32(TTC_OFFSET_TMR_0 + TTC_IER_OFFSET, 0x01);
+
+ *timer_ops = &versal_timers;
+
+ return RET_SUCCESS;
+}
diff --git a/plat/xilinx/versal_net/versal_net_pwr_state.c b/plat/xilinx/versal_net/versal_net_pwr_state.c
new file mode 100644
index 0000000..a87331e
--- /dev/null
+++ b/plat/xilinx/versal_net/versal_net_pwr_state.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stddef.h>
+
+#include <arch.h>
+#include <platform.h>
+#include <psci.h>
+
+/*
+ * State IDs for local power states.
+ */
+#define VERSAL_NET_RETENTION_STATE_ID 1 /* Valid for only CPUs */
+#define VERSAL_NET_OFF_STATE_ID 0 /* Valid for CPUs and Clusters */
+
+/*
+ * Suspend depth definitions for each power state
+ */
+typedef enum {
+ VERSAL_NET_RUN_DEPTH = 0,
+ VERSAL_NET_RETENTION_DEPTH,
+ VERSAL_NET_OFF_DEPTH,
+} suspend_depth_t;
+
+/* The state property array with details of idle state possible for the core */
+static const plat_state_prop_t core_state_prop[] = {
+ {VERSAL_NET_RETENTION_DEPTH, VERSAL_NET_RETENTION_STATE_ID, PSTATE_TYPE_STANDBY},
+ {VERSAL_NET_OFF_DEPTH, VERSAL_NET_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN},
+ {0},
+};
+
+/* The state property array with details of idle state possible for the cluster */
+static const plat_state_prop_t cluster_state_prop[] = {
+ {VERSAL_NET_OFF_DEPTH, VERSAL_NET_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN},
+ {0},
+};
+
+/* The state property array with details of idle state possible for the system level */
+static const plat_state_prop_t system_state_prop[] = {
+ {VERSAL_NET_OFF_DEPTH, VERSAL_NET_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN},
+ {0},
+};
+
+const plat_state_prop_t *plat_get_state_prop(unsigned int level)
+{
+ switch (level) {
+ case MPIDR_AFFLVL0:
+ return core_state_prop;
+ case MPIDR_AFFLVL1:
+ return cluster_state_prop;
+ case MPIDR_AFFLVL2:
+ return system_state_prop;
+ default:
+ return NULL;
+ }
+}
diff --git a/plat/xilinx/versal_net/versal_net_setup.c b/plat/xilinx/versal_net/versal_net_setup.c
new file mode 100644
index 0000000..40fe2c4
--- /dev/null
+++ b/plat/xilinx/versal_net/versal_net_setup.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <arch.h>
+#include <drivers/arm/arm_gic.h>
+#include <drivers/console.h>
+#include <platform.h>
+#include <tftf_lib.h>
+
+#include <platform_def.h>
+#include <util.h>
+
+static const struct {
+ unsigned int cluster_id;
+ unsigned int cpu_id;
+} versal_net_cores[PLATFORM_CORE_COUNT] = {
+ CLUSTER_DEF(0),
+ CLUSTER_DEF(1),
+ CLUSTER_DEF(2),
+ CLUSTER_DEF(3)
+};
+
+
+static const mmap_region_t mmap[] = {
+ MAP_REGION_FLAT(DRAM_BASE + TFTF_NVM_OFFSET, TFTF_NVM_SIZE, MT_MEMORY | MT_RW | MT_NS),
+ MAP_REGION_FLAT(GIC_BASE, GIC_SIZE, MT_DEVICE | MT_RW | MT_NS),
+ MAP_REGION_FLAT(CRASH_CONSOLE_BASE, CRASH_CONSOLE_SIZE, MT_DEVICE | MT_RW | MT_NS),
+ MAP_REGION_FLAT(TTC_BASE, TTC_SIZE, MT_DEVICE | MT_RW | MT_NS),
+ MAP_REGION_FLAT(LPD_IOU_SLCR, LPD_IOU_SLCR_SIZE, MT_DEVICE | MT_RW | MT_NS),
+ {0}
+};
+
+/* Power Domain Tree Descriptor array */
+const unsigned char versal_net_pwr_tree_desc[] = {
+ /* Number of root nodes */
+ 1,
+ /* Number of clusters */
+ PLATFORM_CLUSTER_COUNT,
+ /* Number of children for the first cluster node */
+ PLATFORM_CORE_COUNT_PER_CLUSTER,
+ PLATFORM_CORE_COUNT_PER_CLUSTER,
+ PLATFORM_CORE_COUNT_PER_CLUSTER,
+ PLATFORM_CORE_COUNT_PER_CLUSTER
+};
+
+
+const unsigned char *tftf_plat_get_pwr_domain_tree_desc(void)
+{
+ return versal_net_pwr_tree_desc;
+}
+
+/*
+ * Generate the MPID from the core position.
+ */
+uint64_t tftf_plat_get_mpidr(unsigned int core_pos)
+{
+ assert(core_pos < PLATFORM_CORE_COUNT);
+
+ return (uint64_t)make_mpid(versal_net_cores[core_pos].cluster_id,
+ versal_net_cores[core_pos].cpu_id);
+}
+
+void tftf_plat_arch_setup(void)
+{
+ tftf_plat_configure_mmu();
+}
+
+void tftf_early_platform_setup(void)
+{
+ console_init(CRASH_CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE);
+}
+
+void tftf_platform_setup(void)
+{
+ arm_gic_init(GICC_REG_BASE, GICD_REG_BASE, GICR_REG_BASE);
+ arm_gic_setup_global();
+ arm_gic_setup_local();
+}
+
+const mmap_region_t *tftf_platform_get_mmap(void)
+{
+ return mmap;
+}