commit 503b89a6b2d6ecd039401bd7f6f08f0d3cbb69a6
author Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Thu Jun 19 10:34:11 2025 +0100
committer Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Tue Jul 01 17:53:36 2025 +0100
tree bf4b3f02eabecec15b63e2c5247eb6085b7c5ce8
parent 20c2d74e687556c462b49eb1f8a5e3afc21698cb

fix(lib/pcie): import pcie enumeration helpers from rmm-acs

Import PCIe enumeration helpers from rmm-acs[1] at tag v1.0_REL0_12.24.

This patch adds the missing device enumeration logic added as part of
the initial commit.

This change is verified with FVP default PCI topology. The helper
pcie_init() might need some enhancements for other platforms with
different PCI topology.

[1] https://github.com/ARM-software/cca-rmm-acs

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I46724c458fe0071272fc7bca73d51e27181bb1b4

plat/arm/fvp/fvp_pcie.c

diff --git a/plat/arm/fvp/fvp_pcie.c b/plat/arm/fvp/fvp_pcie.c
index 38bdf39..4bba516 100644
--- a/plat/arm/fvp/fvp_pcie.c
+++ b/plat/arm/fvp/fvp_pcie.c
@@ -27,6 +27,28 @@
 	return &fvp_pcie_cfg;
 }
 
+/* Retrieve platform PCIe bar config values */
+int plat_pcie_get_bar_config(uint64_t *bar64_val, uint64_t *rp_bar64_val,
+			     uint32_t *bar32np_val, uint32_t *bar32p_val,
+			     uint32_t *rp_bar32_val)
+{
+#ifdef __aarch64__
+	assert((bar64_val != NULL) && (rp_bar64_val != NULL) &&
+	       (bar32np_val != NULL) && (bar32p_val != NULL) &&
+	       (rp_bar32_val != NULL));
+
+	*bar64_val = PLATFORM_OVERRIDE_PCIE_BAR64_VALUE;
+	*rp_bar64_val = PLATFORM_OVERRIDE_RP_BAR64_VALUE;
+
+	*bar32np_val = PLATFORM_OVERRIDE_PCIE_BAR32NP_VALUE;
+	*bar32p_val = PLATFORM_OVERRIDE_PCIE_BAR32P_VALUE;
+	*rp_bar32_val = PLATOFRM_OVERRIDE_RP_BAR32_VALUE;
+
+	return 0;
+#endif
+	return -1;
+}
+
 /*
  * Retrieve platform PCIe memory region (Base Platform RevC only)
  */

plat/arm/fvp/include/platform_pcie.h

diff --git a/plat/arm/fvp/include/platform_pcie.h b/plat/arm/fvp/include/platform_pcie.h
index 4b3a0e9..4a2817e 100644
--- a/plat/arm/fvp/include/platform_pcie.h
+++ b/plat/arm/fvp/include/platform_pcie.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2024-2025, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -19,4 +19,11 @@
 #define PLATFORM_PCIE_START_BUS_NUM_0	0x0
 #define PLATFORM_PCIE_END_BUS_NUM_0	0xFF
 
+/* PCIe BAR config parameters*/
+#define PLATFORM_OVERRIDE_PCIE_BAR64_VALUE	0x4000100000
+#define PLATFORM_OVERRIDE_RP_BAR64_VALUE	0x4000000000
+#define PLATFORM_OVERRIDE_PCIE_BAR32NP_VALUE	0x50000000
+#define PLATFORM_OVERRIDE_PCIE_BAR32P_VALUE	0x50600000
+#define PLATOFRM_OVERRIDE_RP_BAR32_VALUE	0x50850000
+
 #endif	/* PLATFORM_PCIE_H */

plat/common/plat_common.c

diff --git a/plat/common/plat_common.c b/plat/common/plat_common.c
index c06ad13..f8524cf 100644
--- a/plat/common/plat_common.c
+++ b/plat/common/plat_common.c
@@ -1,3 +1,4 @@
+
 /*
  * Copyright (c) 2018-2025, Arm Limited. All rights reserved.
  *
@@ -25,6 +26,7 @@
 #pragma weak tftf_plat_reset
 #pragma weak plat_get_prot_regions
 #pragma weak plat_pcie_get_info_table
+#pragma weak plat_pcie_get_bar_config
 #pragma weak plat_get_invalid_addr
 #pragma weak plat_get_dev_region
 
@@ -157,6 +159,13 @@
 	return NULL;
 }
 
+int plat_pcie_get_bar_config(uint64_t *bar64_val, uint64_t *rp_bar64_val,
+			     uint32_t *bar32np_val, uint32_t *bar32p_val,
+			     uint32_t *rp_bar32_val)
+{
+	return -1;
+}
+
 uintptr_t plat_get_invalid_addr(void)
 {
 	return (uintptr_t)0x0;