fix(lib/pcie): import pcie enumeration helpers from rmm-acs
Import PCIe enumeration helpers from rmm-acs[1] at tag v1.0_REL0_12.24.
This patch adds the missing device enumeration logic added as part of
the initial commit.
This change is verified with FVP default PCI topology. The helper
pcie_init() might need some enhancements for other platforms with
different PCI topology.
[1] https://github.com/ARM-software/cca-rmm-acs
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I46724c458fe0071272fc7bca73d51e27181bb1b4
diff --git a/include/lib/pcie/pcie.h b/include/lib/pcie/pcie.h
index d7188a0..7dd165c 100644
--- a/include/lib/pcie/pcie.h
+++ b/include/lib/pcie/pcie.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2024-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -100,7 +100,7 @@
#define CC_BASE_SHIFT 24
void pcie_init(void);
-void pcie_create_info_table(void);
+
pcie_device_bdf_table_t *pcie_get_bdf_table(void);
uint32_t pcie_find_capability(uint32_t bdf, uint32_t cid_type, uint32_t cid,
uint32_t *cid_offset);
diff --git a/include/plat/common/plat_pcie_enum.h b/include/plat/common/plat_pcie_enum.h
new file mode 100644
index 0000000..667fe05
--- /dev/null
+++ b/include/plat/common/plat_pcie_enum.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2025, Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __PLAT_PCIE_ENUM_H__
+#define __PLAT_PCIE_ENUM_H__
+
+#include <stdio.h>
+#include <stdint.h>
+
+/* Header Offset and Type */
+#define HEADER_OFFSET 0xC
+#define TYPE0_HEADER 0
+#define TYPE1_HEADER 1
+
+#define TYPE01_RIDR 0x8
+
+#define DEVICE_ID_OFFSET 16
+
+/* Initial BUS definitions */
+#define PRI_BUS 0
+#define SEC_BUS 1
+#define BUS_NUM_REG_OFFSET 0x18
+
+/* BAR offset */
+#define BAR0_OFFSET 0x10
+#define TYPE1_BAR_MAX_OFF 0x14
+#define TYPE0_BAR_MAX_OFF 0x24
+
+#define BAR_NON_PRE_MEM 0
+#define BAR_PRE_MEM 0x1
+
+#define MEM_BASE32_LIM_MASK 0xFFF00000
+#define MEM_BASE64_LIM_MASK 0xFFFFFFFFFFF00000
+#define NON_PRE_FET_OFFSET 0x20
+#define PRE_FET_OFFSET 0x24
+#define BAR_INCREMENT 0x100000
+
+#define PRI_BUS_CLEAR_MASK 0xFFFFFF00
+
+#define TYPE0_MAX_BARS 6
+#define TYPE1_MAX_BARS 2
+
+/* BAR register masks */
+#define BAR_MIT_MASK 0x1
+#define BAR_MDT_MASK 0x3
+#define BAR_MT_MASK 0x1
+#define BAR_BASE_MASK 0xfffffff
+
+/* BAR register shifts */
+#define BAR_MIT_SHIFT 0
+#define BAR_MDT_SHIFT 1
+#define BAR_MT_SHIFT 3
+#define BAR_BASE_SHIFT 4
+
+/* TYPE 0/1 Cmn Cfg reg offsets and mask*/
+#define TYPE01_CPR 0x34
+#define TYPE01_CPR_MASK 0xff
+#define COMMAND_REG_OFFSET 0x04
+#define REG_ACC_DATA 0x7
+
+#define BAR_MASK 0xFFFFFFF0
+
+#define PCIE_HEADER_TYPE(header_value) ((header_value >> 16) & 0x3)
+#define BUS_NUM_REG_CFG(sub_bus, sec_bus, pri_bus) (sub_bus << 16 | sec_bus << 8 | bus)
+
+#define BAR_REG(bar_reg_value) ((bar_reg_value >> 2) & 0x1)
+#define BAR_MEM(bar_reg_value) ((bar_reg_value & 0xF) >> 3)
+#define REG_MASK_SHIFT(bar_value) ((bar_value & MEM_BASE32_LIM_MASK) >> 16)
+
+#endif /* __PLAT_PCIE_ENUM_H__ */
diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h
index e5032fa..077ccb3 100644
--- a/include/plat/common/platform.h
+++ b/include/plat/common/platform.h
@@ -208,6 +208,11 @@
*/
const struct pcie_info_table *plat_pcie_get_info_table(void);
+/* Retrieve platform PCIe bar config values */
+int plat_pcie_get_bar_config(uint64_t *bar64_val, uint64_t *rp_bar64_val,
+ uint32_t *bar32np_val, uint32_t *bar32p_val,
+ uint32_t *rp_bar32_val);
+
/*
* This function provides an address that is recognized as invalid for use
* as an entry point in the CPU_ON and CPU_SUSPEND calls on this platform.