Merge "fix(xilinx): wire Xilinx platforms in docs"
diff --git a/docs/index.rst b/docs/index.rst
index 4869af1..7e54db2 100644
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -12,6 +12,7 @@
design
implementing-tests
porting/index
+ plat/index
change-log
license
diff --git a/docs/plat/index.rst b/docs/plat/index.rst
new file mode 100644
index 0000000..6f5d9a5
--- /dev/null
+++ b/docs/plat/index.rst
@@ -0,0 +1,17 @@
+Platform Ports
+==============
+
+.. toctree::
+ :maxdepth: 1
+ :caption: Contents
+ :hidden:
+
+ xilinx-versal_net
+ xilinx-versal
+
+This section provides a list of supported upstream *platform ports* and the
+documentation associated with them.
+
+--------------
+
+*Copyright (c) 2024, Arm Limited. All rights reserved.*