feat(rdn2): add support for tftf
Add tftf support for Neoverse Reference Design RD-N2 platform. The RD-N2
platform includes 16 Neoverse N2 CPUs, CMN-700 interconnect, GIC-700 and
SMMU-700.
Signed-off-by: Shriram K <shriram.k@arm.com>
Change-Id: I48802aa6b02bb14d399a61b7c9008572db6d52fc
diff --git a/plat/arm/rdinfra/rdn2/include/platform_def.h b/plat/arm/rdinfra/rdn2/include/platform_def.h
new file mode 100644
index 0000000..a4bd73c
--- /dev/null
+++ b/plat/arm/rdinfra/rdn2/include/platform_def.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <sgi_soc_platform_def_v2.h>
+
+#define PLAT_ARM_CLUSTER_COUNT U(16)
+#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(1)
+#define CSS_SGI_MAX_PE_PER_CPU U(1)
+
+/* GIC-600 & interrupt handling related constants */
+#define PLAT_ARM_GICD_BASE UL(0x30000000)
+#define PLAT_ARM_GICR_BASE UL(0x301C0000)
+#define PLAT_ARM_GICC_BASE UL(0x2C000000)
+
+/* Platform specific page table and MMU setup constants */
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 46)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 46)
+
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/rdinfra/rdn2/platform.mk b/plat/arm/rdinfra/rdn2/platform.mk
new file mode 100644
index 0000000..ed8f252
--- /dev/null
+++ b/plat/arm/rdinfra/rdn2/platform.mk
@@ -0,0 +1,18 @@
+#
+# Copyright (c) 2022, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+include plat/arm/sgi/common/sgi_common.mk
+
+PLAT_INCLUDES += -Iplat/arm/rdinfra/rdn2/include/
+
+PLAT_SOURCES += plat/arm/rdinfra/rdn2/topology.c
+
+PLAT_TESTS_SKIP_LIST := plat/arm/rdinfra/rdn2/tests_to_skip.txt
+
+ifneq ($(CSS_SGI_PLATFORM_VARIANT),0)
+ $(error "CSS_SGI_PLATFORM_VARIANT for RD-N2 should always be 0, \
+ currently set to ${CSS_SGI_PLATFORM_VARIANT}.")
+endif
diff --git a/plat/arm/rdinfra/rdn2/tests_to_skip.txt b/plat/arm/rdinfra/rdn2/tests_to_skip.txt
new file mode 100644
index 0000000..370f2b7
--- /dev/null
+++ b/plat/arm/rdinfra/rdn2/tests_to_skip.txt
@@ -0,0 +1,13 @@
+#
+# Copyright (c) 2022, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# System suspend is not supported as there are no wakeup sources in RD-N2 FVP
+PSCI STAT/Stats test cases after system suspend
+PSCI System Suspend Validation
+
+# The following test cases result in unhandled exception at EL3
+CPU extensions/Use trace buffer control Registers
+CPU extensions/Use trace filter control Registers
diff --git a/plat/arm/rdinfra/rdn2/topology.c b/plat/arm/rdinfra/rdn2/topology.c
new file mode 100644
index 0000000..ad13285
--- /dev/null
+++ b/plat/arm/rdinfra/rdn2/topology.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <plat_topology.h>
+#include <tftf_lib.h>
+
+static const struct {
+ unsigned int cluster_id;
+ unsigned int cpu_id;
+} plat_cores[] = {
+ /* Cluster0: 1 core */
+ { 0, 0 },
+ /* Cluster1: 1 core */
+ { 1, 0 },
+ /* Cluster2: 1 core */
+ { 2, 0 },
+ /* Cluster3: 1 core */
+ { 3, 0 },
+ /* Cluster4: 1 core */
+ { 4, 0 },
+ /* Cluster5: 1 core */
+ { 5, 0 },
+ /* Cluster6: 1 core */
+ { 6, 0 },
+ /* Cluster7: 1 core */
+ { 7, 0 },
+ /* Cluster8: 1 core */
+ { 8, 0 },
+ /* Cluster9: 1 core */
+ { 9, 0 },
+ /* Cluster10: 1 core */
+ { 10, 0 },
+ /* Cluster11: 1 core */
+ { 11, 0 },
+ /* Cluster12: 1 core */
+ { 12, 0 },
+ /* Cluster13: 1 core */
+ { 13, 0 },
+ /* Cluster14: 1 core */
+ { 14, 0 },
+ /* Cluster15: 1 core */
+ { 15, 0 },
+};
+
+/*
+ * The power domain tree descriptor. The cluster power domains are
+ * arranged so that when the PSCI generic code creates the power domain tree,
+ * the indices of the CPU power domain nodes it allocates match the linear
+ * indices returned by plat_core_pos_by_mpidr().
+ */
+const unsigned char plat_pd_tree_desc[] = {
+ /* Number of root nodes */
+ PLAT_ARM_CLUSTER_COUNT,
+ /* Number of children for the 1st node */
+ CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ /* Number of children for the 2nd node */
+ CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ /* Number of children for the 3rd node */
+ CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ /* Number of children for the 4th node */
+ CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ /* Number of children for the 5th node */
+ CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ /* Number of children for the 6th node */
+ CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ /* Number of children for the 7th node */
+ CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ /* Number of children for the 8th node */
+ CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ /* Number of children for the 9th node */
+ CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ /* Number of children for the 10th node */
+ CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ /* Number of children for the 11th node */
+ CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ /* Number of children for the 12th node */
+ CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ /* Number of children for the 13th node */
+ CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ /* Number of children for the 14th node */
+ CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ /* Number of children for the 15th node */
+ CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ /* Number of children for the 16th node */
+ CSS_SGI_MAX_CPUS_PER_CLUSTER
+};
+
+const unsigned char *tftf_plat_get_pwr_domain_tree_desc(void)
+{
+ return plat_pd_tree_desc;
+}
+
+uint64_t tftf_plat_get_mpidr(unsigned int core_pos)
+{
+ unsigned int mpid;
+
+ assert(core_pos < PLATFORM_CORE_COUNT);
+
+ mpid = make_mpid(plat_cores[core_pos].cluster_id,
+ plat_cores[core_pos].cpu_id);
+
+ return (uint64_t)mpid;
+}