feat(smc): add SMCCCv1.3 sve hint bit support in tftf framework
TFTF smc library uses SVE field in trap register to represent SVE
hint flag.
Testcase has to explicitly set this bit using the helper routine
tftf_smc_set_sve_hint(). When set to true, denotes absence of SVE
specific live state on the CPU that implements SVE. Once set to true,
SVE will be disabled in trap register and any SMC made using tftf_smc()
will set FUNCID_SVE_HINT in the SMC function ID.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I13055fe4102cc4e35af1d7091e88327a21778835
diff --git a/spm/cactus/cactus_tests/cactus_test_interrupts.c b/spm/cactus/cactus_tests/cactus_test_interrupts.c
index 6a1092b..4250445 100644
--- a/spm/cactus/cactus_tests/cactus_test_interrupts.c
+++ b/spm/cactus/cactus_tests/cactus_test_interrupts.c
@@ -256,7 +256,17 @@
sp_register_interrupt_handler(sec_interrupt_test_espi_handled,
espi_id);
- ret = tftf_smc(&plat_sip_call);
+
+ /*
+ * Call the low level assembler routine to make the SMC call bypassing
+ * tftf_smc, as tftf_smc will set SVE hint bit in SMC FID when CPU
+ * supports SVE and SVE traps are enabled.
+ *
+ * This can be changed to tftf_smc call once SPMC disregards SVE hint bit
+ * from function identification.
+ */
+ ret = asm_tftf_smc64(plat_sip_call.fid, plat_sip_call.arg1, 0, 0, 0,
+ 0, 0, 0);
if (ret.ret0 == SMC_UNKNOWN) {
ERROR("SiP SMC call not supported\n");