feat(smc): add SMCCCv1.3 sve hint bit support in tftf framework
TFTF smc library uses SVE field in trap register to represent SVE
hint flag.
Testcase has to explicitly set this bit using the helper routine
tftf_smc_set_sve_hint(). When set to true, denotes absence of SVE
specific live state on the CPU that implements SVE. Once set to true,
SVE will be disabled in trap register and any SMC made using tftf_smc()
will set FUNCID_SVE_HINT in the SMC function ID.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I13055fe4102cc4e35af1d7091e88327a21778835
diff --git a/include/lib/extensions/sve.h b/include/lib/extensions/sve.h
index 5670afc..b2cd2a6 100644
--- a/include/lib/extensions/sve.h
+++ b/include/lib/extensions/sve.h
@@ -56,8 +56,11 @@
typedef uint8_t sve_ffr_regs_t[SVE_NUM_FFR_REGS * SVE_FFR_REG_LEN_BYTES]
__aligned(16);
+uint64_t sve_rdvl_1(void);
void sve_config_vq(uint8_t sve_vq);
uint32_t sve_probe_vl(uint8_t sve_max_vq);
+uint64_t sve_read_zcr_elx(void);
+void sve_write_zcr_elx(uint64_t rval);
void sve_z_regs_write(const sve_z_regs_t *z_regs);
void sve_z_regs_write_rand(sve_z_regs_t *z_regs);
@@ -83,23 +86,5 @@
void sve_subtract_arrays(int *dst_array, int *src_array1, int *src_array2,
int array_size);
-#ifdef __aarch64__
-
-/* Returns the SVE implemented VL in bytes (constrained by ZCR_EL3.LEN) */
-static inline uint64_t sve_rdvl_1(void)
-{
- uint64_t vl;
-
- __asm__ volatile(
- ".arch_extension sve\n"
- "rdvl %0, #1;"
- ".arch_extension nosve\n"
- : "=r" (vl)
- );
-
- return vl;
-}
-
-#endif /* __aarch64__ */
#endif /* __ASSEMBLY__ */
#endif /* SVE_H */