commit 417edcad3eb332eca5d7ed70de51cac489a2dca4
author Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Tue Sep 05 17:44:24 2023 +0100
committer Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Thu Nov 30 16:27:24 2023 +0000
tree 520dcd978d3d12003560fd56a66e1c0117521514
parent bbf08c50aca569e517a52d2216c42e7244769a5e

feat(smc): add SMCCCv1.3 sve hint bit support in tftf framework

TFTF smc library uses SVE field in trap register to represent SVE
hint flag.

Testcase has to explicitly set this bit using the helper routine
tftf_smc_set_sve_hint(). When set to true, denotes absence of SVE
specific live state on the CPU that implements SVE. Once set to true,
SVE will be disabled in trap register and any SMC made using tftf_smc()
will set FUNCID_SVE_HINT in the SMC function ID.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I13055fe4102cc4e35af1d7091e88327a21778835