feat: introduce a new test suite supported by EL3 SPMC

A new test suite is being created which is supported by Cactus SP. It
aims to exercise the SIMD context management support in EL3 SPMC.

Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Change-Id: I2a65da8c098b40858a2af0f9012cc225a24e6fcb
diff --git a/tftf/tests/tests-el3-spmc.mk b/tftf/tests/tests-el3-spmc.mk
new file mode 100644
index 0000000..a9c9482
--- /dev/null
+++ b/tftf/tests/tests-el3-spmc.mk
@@ -0,0 +1,28 @@
+#
+# Copyright (c) 2024, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+TESTS_SOURCES	+=							\
+	$(addprefix tftf/tests/runtime_services/secure_service/,	\
+		${ARCH}/ffa_arch_helpers.S				\
+		ffa_helpers.c						\
+		spm_common.c						\
+		spm_test_helpers.c					\
+	)
+
+ifeq (${ARCH},aarch64)
+TESTS_SOURCES   +=                                                      \
+        $(addprefix tftf/tests/runtime_services/secure_service/,        \
+	  test_spm_simd.c					\
+	 )
+
+TESTS_SOURCES	+=							\
+	$(addprefix tftf/tests/runtime_services/secure_service/,	\
+		test_ffa_smccc.c					\
+		test_ffa_smccc_asm.S					\
+	)
+
+TESTS_SOURCES   += lib/extensions/fpu/fpu.c
+endif
diff --git a/tftf/tests/tests-el3-spmc.xml b/tftf/tests/tests-el3-spmc.xml
new file mode 100644
index 0000000..d194fab
--- /dev/null
+++ b/tftf/tests/tests-el3-spmc.xml
@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<!--
+  Copyright (c) 2024, Arm Limited. All rights reserved.
+
+  SPDX-License-Identifier: BSD-3-Clause
+-->
+
+<testsuites>
+
+  <testsuite name="SIMD,SVE Registers context"
+             description="Validate context switch between NWd and SWd" >
+     <testcase name="Check that SIMD registers context is preserved"
+               function="test_simd_vectors_preserved" />
+     <testcase name="Check that SVE registers context is preserved"
+               function="test_sve_vectors_preserved" />
+     <testcase name="Check that SVE operations in NWd are unaffected by SWd"
+               function="test_sve_vectors_operations" />
+     <testcase name="Enter SPMC with SME SSVE enabled"
+               function="test_sme_streaming_sve" />
+     <testcase name="Enter SPMC with SME ZA enabled"
+               function="test_sme_za" />
+     <testcase name="Enter SPMC with SME SM+ZA enabled"
+               function="test_sme_streaming_sve_za" />
+  </testsuite>
+
+</testsuites>