Merge "TFTF: Add missing D-cache invalidation"
diff --git a/tftf/framework/aarch32/entrypoint.S b/tftf/framework/aarch32/entrypoint.S
index 1f302fa..eaa0788 100644
--- a/tftf/framework/aarch32/entrypoint.S
+++ b/tftf/framework/aarch32/entrypoint.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -19,6 +19,18 @@
 	bl	arch_init
 
 	/* --------------------------------------------------------------------
+	 * Invalidate the RW memory used by TFTF image.
+	 * This is done to safeguard against possible corruption of this
+	 * memory by dirty cache lines in a system cache as a result of use
+	 * by an earlier boot loader stage.
+	 * --------------------------------------------------------------------
+	 */
+	ldr	r0, =__DATA_START__
+	ldr	r1, =__DATA_END__
+	sub	r1, r1, r0
+	bl	inv_dcache_range
+
+	/* --------------------------------------------------------------------
 	 * This code is expected to be executed only by the primary CPU.
 	 * Save the mpid for the first core that executes and if a secondary
 	 * CPU has lost its way make it spin forever.
diff --git a/tftf/framework/aarch64/entrypoint.S b/tftf/framework/aarch64/entrypoint.S
index 0a4afe0..81fd207 100644
--- a/tftf/framework/aarch64/entrypoint.S
+++ b/tftf/framework/aarch64/entrypoint.S
@@ -20,6 +20,18 @@
 	bl	arch_init
 
 	/* --------------------------------------------------------------------
+	 * Invalidate the RW memory used by TFTF image.
+	 * This is done to safeguard against possible corruption of this
+	 * memory by dirty cache lines in a system cache as a result of use
+	 * by an earlier boot loader stage.
+	 * --------------------------------------------------------------------
+	 */
+	adr	x0, __DATA_START__
+	adr	x1, __DATA_END__
+	sub	x1, x1, x0
+	bl	inv_dcache_range
+
+	/* --------------------------------------------------------------------
 	 * This code is expected to be executed only by the primary CPU.
 	 * Save the mpid for the first core that executes and if a secondary
 	 * CPU has lost its way make it spin forever.