commit 2f30f1030f186760b20cd06b59832e332b2bdd0a
author AlexeiFedorov <Alexei.Fedorov@arm.com> Mon Mar 13 19:37:46 2023 +0000
committer Soby Mathew <soby.mathew@arm.com> Fri Mar 31 11:41:56 2023 +0200
tree e06899ba1be405650b4a15603429900dac67ccc2
parent 2eb601b98a245df8a31e670a7dc322c2e8f153cf

feat(rme): add PMU Realm tests

This patch adds Realm PMU payload tests with
PMU interrupt handling.

Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: I86ef96252e04c57db385e129227cc0d7dcd1fec2

include/drivers/arm/gic_v3.h

diff --git a/include/drivers/arm/gic_v3.h b/include/drivers/arm/gic_v3.h
index 0346a23..e164103 100644
--- a/include/drivers/arm/gic_v3.h
+++ b/include/drivers/arm/gic_v3.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2023, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -83,6 +83,25 @@
 #define IGRPEN1_EL1_ENABLE_SHIFT	0
 #define IGRPEN1_EL1_ENABLE_BIT		(1 << IGRPEN1_EL1_ENABLE_SHIFT)
 
+/* ICH_ICH_LR<n>_EL2 definitions */
+#define ICH_LRn_EL2_STATE_Invalid		(0UL << 62)
+#define ICH_LRn_EL2_STATE_Pending		(1UL << 62)
+#define ICH_LRn_EL2_STATE_Active		(2UL << 62)
+#define ICH_LRn_EL2_STATE_Pending_Active	(3UL << 62)
+#define ICH_LRn_EL2_Group_0			(0UL << 60)
+#define ICH_LRn_EL2_Group_1			(1UL << 60)
+#define ICH_LRn_EL2_Priority_SHIFT		48
+#define ICH_LRn_EL2_Priority_MASK		0xFF
+#define ICH_LRn_EL2_vINTID_SHIFT		0
+#define ICH_LRn_EL2_vINTID_MASK			0xFFFF
+
+/* ICV_CTLR_EL1 definitions */
+#define ICV_CTLR_EL1_PRIbits_SHIFT		8
+#define ICV_CTLR_EL1_PRIbits_MASK		7
+
+/* ICV_IGRPEN1_EL1 definition */
+#define ICV_IGRPEN1_EL1_Enable			1UL
+
 /* The highest affinity 0 that can be a SGI target*/
 #define SGI_TARGET_MAX_AFF0		16