feat(trf): add trace filter control registers access test
Added a test to read trace filter control registers to ensure that EL3
is giving permission to non-secure EL2 to access these registers.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I9354d8592bd187206add717b9d3b0206382a06d3
diff --git a/tftf/tests/tests-cpu-extensions.xml b/tftf/tests/tests-cpu-extensions.xml
index d6b3d00..a0d2c9a 100644
--- a/tftf/tests/tests-cpu-extensions.xml
+++ b/tftf/tests/tests-cpu-extensions.xml
@@ -21,6 +21,7 @@
<testcase name="Use FGT Registers" function="test_fgt_enabled" />
<testcase name="Use ECV Registers" function="test_ecv_enabled" />
<testcase name="Use trace buffer control Registers" function="test_trbe_enabled" />
+ <testcase name="Use trace filter control Registers" function="test_trf_enabled" />
</testsuite>
<testsuite name="ARM_ARCH_SVC" description="Arm Architecture Service tests">