ta: os_test: declare undefined instruction for RISC-V
RISC-V instruction size is 32-bits, 0x0 triggers an illegal
instruction exception.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
diff --git a/ta/os_test/os_test.c b/ta/os_test/os_test.c
index 7a74c92..b95c0a1 100644
--- a/ta/os_test/os_test.c
+++ b/ta/os_test/os_test.c
@@ -981,6 +981,8 @@
__asm__(".word 0x0");
#elif defined(ARM32)
__asm__(".word 0xe7ffffff");
+#elif defined(RV64) || defined(RV32)
+ __asm__(".word 0x0");
#else
#error "Unsupported architecture"
#endif
@@ -1529,5 +1531,3 @@
TEE_Free(p);
return TEE_ERROR_GENERIC;
}
-
-