| commit | 7b8c75546bd14849589723e26aba6efb1782cc4b | [log] [tgz] |
|---|---|---|
| author | Gabriel Fernandez <gabriel.fernandez@foss.st.com> | Tue Jun 03 15:13:02 2025 +0200 |
| committer | Jerome Forissier <jerome@forissier.org> | Wed Jun 18 12:39:24 2025 +0200 |
| tree | 3dd661822735d0e247fe3bfde18f038a8356bb47 | |
| parent | 678a558fd2617dd957b862f521ce3e8481636010 [diff] |
clk: stm32mp25: force ARM_DIVSEL for flexgen63 config at 400MHz
When clkext2f is selected as the clock source, a division by 2
must be applied to the SSC register (A3x_SS_CHGCLKREQ.ARM_DIVSEL)
because the clkext2f frequency of 400MHz is not supported.
This patch also rename the function stm32mp2_a35_ss_on_hsi to
stm32mp2_a35_ss_on_bypass to be aligned with reference manual.
Fixes: 28c10f9efa6a ("clk: stm32mp25: Introduce STM32MP25 clocks platform")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
This git contains source code for the secure side implementation of OP-TEE project.
All official OP-TEE documentation has moved to http://optee.readthedocs.io.
// OP-TEE core maintainers