| commit | 5ee429d5b99102a643164b86bbd0c3c81735c402 | [log] [tgz] |
|---|---|---|
| author | Yu-Chien Peter Lin <peter.lin@sifive.com> | Mon Jun 23 01:03:41 2025 +0800 |
| committer | Jerome Forissier <jerome@forissier.org> | Mon Jun 23 11:27:40 2025 +0200 |
| tree | 5c6d0fca3830a4c4505d88b245170a0854c46d67 | |
| parent | 5c4fede57b34f61721c73e3d2f8fedf11aede47f [diff] |
core: riscv: fix hartid at secondary hart entry point
The a0 register is corrupted during enable_mmu, so get
secondary hartid from s0 instead.
Fixes: 29661368f51d ("core: riscv: preserve hartid in s0 register at entry point")
Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
This git contains source code for the secure side implementation of OP-TEE project.
All official OP-TEE documentation has moved to http://optee.readthedocs.io.
// OP-TEE core maintainers