core: riscv: preserve hartid in s0 register at entry point

The hartid is initially passed in a0 register. Since we
will introduce function calls in subsequent patches and
a0 is caller-saved per RISC-V calling convention, preserve
the hart ID in s0 (callee-saved) to avoid unnecessary
save-restore operations when making function calls.

Also, use temporary registers instead in set_tp, makes
it more consistent with set_sp.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Suggested-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
1 file changed
tree: 7ffa273fabda14d77b27541d4258fc80768b3bbe
  1. .devcontainer/
  2. .github/
  3. .vscode/
  4. core/
  5. keys/
  6. ldelf/
  7. lib/
  8. mk/
  9. scripts/
  10. ta/
  11. .checkpatch.conf
  12. .clang-format
  13. .gitattributes
  14. .gitignore
  15. CHANGELOG.md
  16. LICENSE
  17. MAINTAINERS
  18. Makefile
  19. README.md
  20. typedefs.checkpatch
README.md

OP-TEE Trusted OS

This git contains source code for the secure side implementation of OP-TEE project.

All official OP-TEE documentation has moved to http://optee.readthedocs.io.

// OP-TEE core maintainers