qemu_v8: OP-TEE SP fix uart interrupt config
The UART interrupt was configured as level-triggered prior to this
patch, but it should be edge-triggered. So fix the level configuration.
Suggested-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
diff --git a/qemu_v8/optee_sp_manifest.dts b/qemu_v8/optee_sp_manifest.dts
index 9b7dda4..f9968f7 100644
--- a/qemu_v8/optee_sp_manifest.dts
+++ b/qemu_v8/optee_sp_manifest.dts
@@ -48,8 +48,8 @@
base-address = <0x00000000 0x09040000>;
pages-count = <1>;
attributes = <0x3>; /* read-write */
- /* SPI, level-triggered, secure, priority=1 */
- interrupts = <0x28 0xb01>;
+ /* SPI, edge-triggered, secure, priority=1 */
+ interrupts = <0x28 0x901>;
};
};
};