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authorJose Marinho <jose.marinho@arm.com>2019-10-18 11:39:01 +0100
committerOlivier Deprez <olivier.deprez@arm.com>2020-07-22 15:38:20 +0000
commitab1081d2036716cb1a5aabe4dde837b5f6fd3fc6 (patch)
treeaf98c7c97f8f6aac2e86f89230c706be6fd8edb4
parentcc071f181d296ec08f7367ec99a3cfdde03ba593 (diff)
downloadhafnium-ab1081d2036716cb1a5aabe4dde837b5f6fd3fc6.tar.gz
aarch64: enable secure EL1/EL0 stage-1 translation regime
VSTTBR_EL2 set to the the value of VTTBR_EL2 VSTCR_EL2 set to the the value of VTCR_EL2 Change-Id: I6a893a690650f73412a0c238ad231c572aba16ad Signed-off-by: Jose Marinho <jose.marinho@arm.com> Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
-rw-r--r--src/arch/aarch64/hypervisor/exceptions.S5
-rw-r--r--src/arch/aarch64/hypervisor/hypervisor_entry.S6
-rw-r--r--src/arch/aarch64/msr.h18
3 files changed, 29 insertions, 0 deletions
diff --git a/src/arch/aarch64/hypervisor/exceptions.S b/src/arch/aarch64/hypervisor/exceptions.S
index 6253ab6..beecc64 100644
--- a/src/arch/aarch64/hypervisor/exceptions.S
+++ b/src/arch/aarch64/hypervisor/exceptions.S
@@ -7,6 +7,7 @@
*/
#include "hf/arch/offsets.h"
+#include "msr.h"
#include "exception_macros.S"
/**
@@ -430,6 +431,10 @@ vcpu_restore_lazy_and_run:
msr cnthctl_el2, x26
msr vttbr_el2, x27
+#if SECURE_WORLD == 1
+ msr MSR_VSTTBR_EL2, x27
+#endif
+
ldp x4, x5, [x28], #16
msr mdcr_el2, x4
msr mdscr_el1, x5
diff --git a/src/arch/aarch64/hypervisor/hypervisor_entry.S b/src/arch/aarch64/hypervisor/hypervisor_entry.S
index 309a2f0..364e893 100644
--- a/src/arch/aarch64/hypervisor/hypervisor_entry.S
+++ b/src/arch/aarch64/hypervisor/hypervisor_entry.S
@@ -7,6 +7,7 @@
*/
#include "hf/arch/offsets.h"
+#include "msr.h"
/**
* Called only on first boot after the image has been relocated and BSS zeroed.
@@ -120,6 +121,11 @@ mm_enable:
msr ttbr0_el2, x1
msr vtcr_el2, x2
+
+#if SECURE_WORLD == 1
+ msr MSR_VSTCR_EL2, x2
+#endif
+
msr mair_el2, x3
msr tcr_el2, x4
diff --git a/src/arch/aarch64/msr.h b/src/arch/aarch64/msr.h
index 564821f..98da341 100644
--- a/src/arch/aarch64/msr.h
+++ b/src/arch/aarch64/msr.h
@@ -6,6 +6,8 @@
* https://opensource.org/licenses/BSD-3-Clause.
*/
+#ifndef __ASSEMBLER__
+
#pragma once
#include <stddef.h>
@@ -40,6 +42,8 @@
: "rZ"((uintreg_t)(value))); \
})
+#endif /* __ASSEMBLER__ */
+
/*
* Encodings for registers supported after Armv8.0.
* We aim to build one binary that supports a variety of platforms, therefore,
@@ -60,3 +64,17 @@
* This register enables and disables LORegions (Armv8.1).
*/
#define MSR_LORC_EL1 S3_0_C10_C4_3
+
+/*
+ * Registers supported from Armv8.4 onwards.
+ */
+
+/*
+ * VSTTBR_EL2, Virtualization Secure Translation Table Base Register
+ */
+#define MSR_VSTTBR_EL2 S3_4_C2_C6_0
+
+/*
+ * VSTCR_EL2, Virtualization Secure Translation Control Register
+ */
+#define MSR_VSTCR_EL2 S3_4_C2_C6_2