aboutsummaryrefslogtreecommitdiff
path: root/platform/ext/target/arm/musca_b1/sse_200/Native_Driver/uart_pl011_drv.c
blob: 01feaa4fdd89dd4ee7461f00630ff1b18e1f1d0b (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
/*
 * Copyright (c) 2016-2018 Arm Limited
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

#include "uart_pl011_drv.h"

#include <stddef.h>
#include "cmsis_compiler.h"

#define FREQ_IRLPBAUD16_MIN             (1420000u)     /* 1.42 MHz */
#define FREQ_IRLPBAUD16_MAX             (2120000u)     /* 2.12 MHz */
#define SAMPLING_FACTOR                 (16u)
#define UART_PL011_FBRD_WIDTH           (6u)

/**
 * \brief UART PL011 register map structure
 */
struct _uart_pl011_reg_map_t {
    volatile uint32_t uartdr;          /*!< Offset: 0x000 (R/W) Data register */
    union {
        volatile uint32_t uartrsr;
                /*!< Offset: 0x004 (R/ ) Receive status register */
        volatile uint32_t uartecr;
                /*!< Offset: 0x004 ( /W) Error clear register */
    };
    volatile uint32_t reserved_0[4];   /*!< Offset: 0x008-0x014 Reserved */
    volatile uint32_t uartfr;          /*!< Offset: 0x018 (R/ ) Flag register */
    volatile uint32_t reserved_1;      /*!< Offset: 0x01C       Reserved */
    volatile uint32_t uartilpr;
                /*!< Offset: 0x020 (R/W) IrDA low-power counter register */
    volatile uint32_t uartibrd;
                /*!< Offset: 0x024 (R/W) Integer baud rate register */
    volatile uint32_t uartfbrd;
                /*!< Offset: 0x028 (R/W) Fractional baud rate register */
    volatile uint32_t uartlcr_h;
                /*!< Offset: 0x02C (R/W) Line control register */
    volatile uint32_t uartcr;
                /*!< Offset: 0x030 (R/W) Control register */
    volatile uint32_t uartifls;
                /*!< Offset: 0x034 (R/W) Interrupt FIFO level select register */
    volatile uint32_t uartimsc;
                /*!< Offset: 0x038 (R/W) Interrupt mask set/clear register */
    volatile uint32_t uartris;
                /*!< Offset: 0x03C (R/ ) Raw interrupt status register */
    volatile uint32_t uartmis;
                /*!< Offset: 0x040 (R/ ) Masked interrupt status register */
    volatile uint32_t uarticr;
                /*!< Offset: 0x044 ( /W) Interrupt clear register */
    volatile uint32_t uartdmacr;
                /*!< Offset: 0x048 (R/W) DMA control register */
    volatile uint32_t reserved_2[13];  /*!< Offset: 0x04C-0x07C Reserved */
    volatile uint32_t reserved_3[4];
                /*!< Offset: 0x080-0x08C Reserved for test purposes */
    volatile uint32_t reserved_4[976]; /*!< Offset: 0x090-0xFCC Reserved */
    volatile uint32_t reserved_5[4];
                /*!< Offset: 0xFD0-0xFDC Reserved for future ID expansion */
    volatile uint32_t uartperiphid0;
                /*!< Offset: 0xFE0 (R/ ) UARTPeriphID0 register */
    volatile uint32_t uartperiphid1;
                /*!< Offset: 0xFE4 (R/ ) UARTPeriphID1 register */
    volatile uint32_t uartperiphid2;
                /*!< Offset: 0xFE8 (R/ ) UARTPeriphID2 register */
    volatile uint32_t uartperiphid3;
                /*!< Offset: 0xFEC (R/ ) UARTPeriphID3 register */
    volatile uint32_t uartpcellid0;
                /*!< Offset: 0xFF0 (R/ ) UARTPCellID0 register */
    volatile uint32_t uartpcellid1;
                /*!< Offset: 0xFF4 (R/ ) UARTPCellID1 register */
    volatile uint32_t uartpcellid2;
                /*!< Offset: 0xFF8 (R/ ) UARTPCellID2 register */
    volatile uint32_t uartpcellid3;
                /*!< Offset: 0xFFC (R/ ) UARTPCellID3 register */
};

#define UART_PL011_UARTFR_CTS_MASK (                    \
            0x1u<<UART_PL011_UARTFR_CTS_OFF)
#define UART_PL011_UARTFR_DSR_MASK (                    \
            0x1u<<UART_PL011_UARTFR_DSR_OFF)
#define UART_PL011_UARTFR_DCD_MASK (                    \
            0x1u<<UART_PL011_UARTFR_DCD_OFF)
#define UART_PL011_UARTFR_BUSYBIT (                     \
            0x1u<<UART_PL011_UARTFR_BUSYBIT_OFF)
#define UART_PL011_UARTFR_RX_FIFO_EMPTY (               \
            0x1u<<UART_PL011_UARTFR_RX_FIFO_EMPTY_OFF)
#define UART_PL011_UARTFR_TX_FIFO_FULL (                \
            0x1u<<UART_PL011_UARTFR_TX_FIFO_FULL_OFF)
#define UART_PL011_UARTFR_RI_MASK (                     \
            0x1u<<UART_PL011_UARTFR_RI_OFF)

#define UART_PL011_UARTLCR_H_BRK_MASK (                 \
            0x1u<<UART_PL011_UARTLCR_H_BRK_OFF)
#define UART_PL011_UARTLCR_H_PARITY_MASK (              \
            0x1u<<UART_PL011_UARTLCR_H_PEN_OFF          \
          | 0x1u<<UART_PL011_UARTLCR_H_EPS_OFF          \
          | 0x1u<<UART_PL011_UARTLCR_H_SPS_OFF)
#define UART_PL011_UARTLCR_H_STOPBIT_MASK (             \
            0x1u<<UART_PL011_UARTLCR_H_STP2_OFF)
#define UART_PL011_UARTLCR_H_FEN_MASK (                 \
            0x1u<<UART_PL011_UARTLCR_H_FEN_OFF)
#define UART_PL011_UARTLCR_H_WLEN_MASK (                \
            0x3u<<UART_PL011_UARTLCR_H_WLEN_OFF)
#define UART_PL011_FORMAT_MASK (                        \
            UART_PL011_UARTLCR_H_PARITY_MASK            \
          | UART_PL011_UARTLCR_H_STOPBIT_MASK           \
          | UART_PL011_UARTLCR_H_WLEN_MASK)

#define UART_PL011_UARTCR_EN_MASK (                     \
            0x1u<<UART_PL011_UARTCR_UARTEN_OFF)
#define UART_PL011_UARTCR_SIREN_MASK (                  \
            0x1u<<UART_PL011_UARTCR_SIREN_OFF)
#define UART_PL011_UARTCR_SIRLP_MASK (                  \
            0x1u<<UART_PL011_UARTCR_SIRLP_OFF)
#define UART_PL011_UARTCR_LBE_MASK (                    \
            0x1u<<UART_PL011_UARTCR_LBE_OFF)
#define UART_PL011_UARTCR_TX_EN_MASK (                  \
            0x1u<<UART_PL011_UARTCR_TXE_OFF)
#define UART_PL011_UARTCR_RX_EN_MASK (                  \
            0x1u<<UART_PL011_UARTCR_RXE_OFF)
#define UART_PL011_UARTCR_DTR_MASK (                    \
            0x1u<<UART_PL011_UARTCR_DTR_OFF)
#define UART_PL011_UARTCR_RTS_MASK (                    \
            0x1u<<UART_PL011_UARTCR_RTS_OFF)
#define UART_PL011_UARTCR_OUT1_MASK (                   \
            0x1u<<UART_PL011_UARTCR_OUT1_OFF)
#define UART_PL011_UARTCR_OUT2_MASK (                   \
            0x1u<<UART_PL011_UARTCR_OUT2_OFF)
#define UART_PL011_UARTCR_RTSE_MASK (                   \
            0x1u<<UART_PL011_UARTCR_RTSE_OFF)
#define UART_PL011_UARTCR_CTSE_MASK (                   \
            0x1u<<UART_PL011_UARTCR_CTSE_OFF)

#define UART_PL011_UARTIFLS_TX_FIFO_LVL_MASK (          \
            0x7u<<UART_PL011_UARTIFLS_TX_OFF)
#define UART_PL011_UARTIFLS_RX_FIFO_LVL_MASK (          \
            0x7u<<UART_PL011_UARTIFLS_RX_OFF)

#define UART_PL011_UARTDMACR_RX_MASK (                  \
            0x1u<<UART_PL011_UARTDMACR_RXEN_OFF         \
          | 0x1u<<UART_PL011_UARTDMACR_ON_ERR_OFF)
#define UART_PL011_UARTDMACR_TX_MASK (                  \
            0x1u<<UART_PL011_UARTDMACR_TXEN_OFF)

/* Default register values of UART PL011 */
#define UART_PL011_DATA_REG_RESET_VALUE     (0x0u)
#define UART_PL011_ECR_REG_CLEAR_VALUE      (0xFFu)
#define UART_PL011_ILPR_REG_RESET_VALUE     (0x0u)
#define UART_PL011_IBRD_REG_RESET_VALUE     (0x0u)
#define UART_PL011_FBRD_REG_RESET_VALUE     (0x0u)
#define UART_PL011_LCR_H_REG_RESET_VALUE    (0x0u)
#define UART_PL011_CR_REG_RESET_VALUE       (0x0300u)
#define UART_PL011_IFLS_REG_RESET_VALUE     (0x12u)
#define UART_PL011_IMSC_REG_RESET_VALUE     (0x0u)
#define UART_PL011_ICR_REG_CLEAR_VALUE      (0x7FFu)
#define UART_PL011_DMACR_REG_RESET_VALUE    (0x0u)

static void _uart_pl011_enable(struct _uart_pl011_reg_map_t* p_uart)
{
    p_uart->uartcr |=  UART_PL011_UARTCR_EN_MASK;
}

static void _uart_pl011_disable(struct _uart_pl011_reg_map_t* p_uart)
{
    p_uart->uartcr &= ~UART_PL011_UARTCR_EN_MASK;
}

static bool _uart_pl011_is_enabled(struct _uart_pl011_reg_map_t* p_uart)
{
    return (bool)(p_uart->uartcr & UART_PL011_UARTCR_EN_MASK);
}

static void _uart_pl011_enable_fifo(struct _uart_pl011_reg_map_t* p_uart)
{
    p_uart->uartlcr_h |= UART_PL011_UARTLCR_H_FEN_MASK;
}

static void _uart_pl011_disable_fifo(struct _uart_pl011_reg_map_t* p_uart)
{
    p_uart->uartlcr_h &= ~UART_PL011_UARTLCR_H_FEN_MASK;
}

static bool _uart_pl011_is_fifo_enabled(struct _uart_pl011_reg_map_t* p_uart)
{
    return (bool)(p_uart->uartlcr_h & UART_PL011_UARTLCR_H_FEN_MASK);
}

static bool _uart_pl011_is_busy(struct _uart_pl011_reg_map_t* p_uart)
{
    return (bool)(p_uart->uartfr & UART_PL011_UARTFR_BUSYBIT);
}

static enum uart_pl011_error_t _uart_pl011_set_baudrate(
                    struct _uart_pl011_reg_map_t* p_uart,
                    uint32_t clk, uint32_t baudrate)
{
    /* Avoiding float calculations, bauddiv is left shifted by 6 */
    uint64_t bauddiv = (((uint64_t)clk)<<UART_PL011_FBRD_WIDTH)
                       /(SAMPLING_FACTOR*baudrate);

    /* Valid bauddiv value
     * uart_clk (min) >= 16 x baud_rate (max)
     * uart_clk (max) <= 16 x 65535 x baud_rate (min)
     */
    if((bauddiv < (1u<<UART_PL011_FBRD_WIDTH))
       || (bauddiv > (65535u<<UART_PL011_FBRD_WIDTH))) {
        return UART_PL011_ERR_INVALID_BAUD;
    }

    p_uart->uartibrd = (uint32_t)(bauddiv >> UART_PL011_FBRD_WIDTH);
    p_uart->uartfbrd = (uint32_t)(bauddiv &
                                 ((1u << UART_PL011_FBRD_WIDTH) - 1u));

    __DMB();

    /* In order to internally update the contents of uartibrd or uartfbrd, a
     * uartlcr_h write must always be performed at the end
     * ARM DDI 0183F, Pg 3-13
     */
    p_uart->uartlcr_h = p_uart->uartlcr_h;

    return UART_PL011_ERR_NONE;
}

static void _uart_pl011_set_format(struct _uart_pl011_reg_map_t* p_uart,
                    enum uart_pl011_wlen_t word_len,
                    enum uart_pl011_parity_t parity,
                    enum uart_pl011_stopbit_t stop_bits)
{
    uint32_t ctrl_reg = p_uart->uartlcr_h & ~(UART_PL011_FORMAT_MASK);

    /* Making sure other bit are not changed */
    word_len  &= UART_PL011_UARTLCR_H_WLEN_MASK;
    parity    &= UART_PL011_UARTLCR_H_PARITY_MASK;
    stop_bits &= UART_PL011_UARTLCR_H_STOPBIT_MASK;

    p_uart->uartlcr_h = ctrl_reg | word_len | parity | stop_bits;

}

static void _uart_pl011_set_cr_bit(struct _uart_pl011_reg_map_t* p_uart,
                    uint32_t mask)
{
    bool uart_enabled = _uart_pl011_is_enabled(p_uart);
    bool fifo_enabled = _uart_pl011_is_fifo_enabled(p_uart);

    /* UART must be disabled before any Control Register or
     * Line Control Register are reprogrammed */
    _uart_pl011_disable(p_uart);

    /* Flush the transmit FIFO by disabling bit 4 (FEN) in
     * the line control register (UARTCLR_H) */
    _uart_pl011_disable_fifo(p_uart);

    p_uart->uartcr |= (mask);

    /* Enabling the FIFOs if previously enabled */
    if(fifo_enabled) {
        _uart_pl011_enable_fifo(p_uart);
    }

    /* Enabling the UART if previously enabled */
    if(uart_enabled) {
        _uart_pl011_enable(p_uart);
    }
}

static void _uart_pl011_clear_cr_bit(struct _uart_pl011_reg_map_t* p_uart,
                    uint32_t mask)
{
    bool uart_enabled = _uart_pl011_is_enabled(p_uart);
    bool fifo_enabled = _uart_pl011_is_fifo_enabled(p_uart);

    /* UART must be disabled before any Control Register or
     * Line Control Register are reprogrammed */
    _uart_pl011_disable(p_uart);

    /* Flush the transmit FIFO by disabling bit 4 (FEN) in
     * the line control register (UARTCLR_H) */
    _uart_pl011_disable_fifo(p_uart);

    p_uart->uartcr &= ~(mask);

    /* Enabling the FIFOs if previously enabled */
    if(fifo_enabled) {
        _uart_pl011_enable_fifo(p_uart);
    }

    /* Enabling the UART if previously enabled */
    if(uart_enabled) {
        _uart_pl011_enable(p_uart);
    }
}

static void _uart_pl011_set_lcr_h_bit(struct _uart_pl011_reg_map_t* p_uart,
                    uint32_t mask)
{
    bool uart_enabled = _uart_pl011_is_enabled(p_uart);

    /* UART must be disabled before any Control Register or
     * Line Control Register are reprogrammed */
    _uart_pl011_disable(p_uart);

    p_uart->uartlcr_h |= (mask);

    /* Enabling the UART if previously enabled */
    if(uart_enabled) {
        _uart_pl011_enable(p_uart);
    }
}

static void _uart_pl011_clear_lcr_h_bit(struct _uart_pl011_reg_map_t* p_uart,
                    uint32_t mask)
{
    bool uart_enabled = _uart_pl011_is_enabled(p_uart);

    /* UART must be disabled before any Control Register or
     * Line Control Register are reprogrammed */
    _uart_pl011_disable(p_uart);

    p_uart->uartlcr_h &= ~(mask);

    /* Enabling the UART if previously enabled */
    if(uart_enabled) {
        _uart_pl011_enable(p_uart);
    }
}

static void _uart_pl011_reset_regs(struct _uart_pl011_reg_map_t* p_uart)
{
    /* Restore the default value of UART registers, the registers which
     * are not listed below are Read-Only */

    /* Will disable the UART */
    p_uart->uartcr      = UART_PL011_CR_REG_RESET_VALUE;
    p_uart->uartdr      = UART_PL011_DATA_REG_RESET_VALUE;
    /* Clear all the errors */
    p_uart->uartecr     = UART_PL011_ECR_REG_CLEAR_VALUE;
    p_uart->uartilpr    = UART_PL011_ILPR_REG_RESET_VALUE;
    p_uart->uartibrd    = UART_PL011_IBRD_REG_RESET_VALUE;
    p_uart->uartfbrd    = UART_PL011_FBRD_REG_RESET_VALUE;
    p_uart->uartlcr_h   = UART_PL011_LCR_H_REG_RESET_VALUE;
    p_uart->uartifls    = UART_PL011_IFLS_REG_RESET_VALUE;
    p_uart->uartimsc    = UART_PL011_IMSC_REG_RESET_VALUE;
    /* Clear all the interrupts */
    p_uart->uarticr     = UART_PL011_ICR_REG_CLEAR_VALUE;
    p_uart->uartdmacr   = UART_PL011_DMACR_REG_RESET_VALUE;
}

enum uart_pl011_error_t uart_pl011_init(struct uart_pl011_dev_t* dev,
                    uint32_t uart_clk)
{
    enum uart_pl011_error_t err;

    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    uint32_t def_baud = dev->cfg->def_baudrate;

    if(uart_clk == 0) {
        return UART_PL011_ERR_INVALID_ARG;
    }

    if(def_baud == 0) {
        return UART_PL011_ERR_INVALID_BAUD;
    }

    /* Updating the system clock */
    dev->data->uart_clk = uart_clk;

    /* Setting the default baudrate */
    err = _uart_pl011_set_baudrate(p_uart, uart_clk, def_baud);

    if(err != UART_PL011_ERR_NONE) {
        return err;
    }

    /* Setting the default character format */
    _uart_pl011_set_format(p_uart, dev->cfg->def_wlen,
                                   dev->cfg->def_parity,
                                   dev->cfg->def_stopbit);

    /* Enabling the FIFOs */
    _uart_pl011_enable_fifo(p_uart);

    dev->data->state = UART_PL011_INITIALIZED;

    return UART_PL011_ERR_NONE;
}

void uart_pl011_uninit(struct uart_pl011_dev_t* dev)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    while(_uart_pl011_is_busy(p_uart));

    /* Disable and restore the default configuration of the peripheral */
    _uart_pl011_reset_regs(p_uart);

    dev->data->state = UART_PL011_UNINITIALIZED;

    return;
}

enum uart_pl011_state_t uart_pl011_get_state(struct uart_pl011_dev_t* dev)
{
    return dev->data->state;
}

enum uart_pl011_error_t uart_pl011_set_baudrate(
                    struct uart_pl011_dev_t* dev, uint32_t baudrate)
{
    enum uart_pl011_error_t err = UART_PL011_ERR_NONE;

    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    bool uart_enabled = _uart_pl011_is_enabled(p_uart);

    if(uart_pl011_get_state(dev) != UART_PL011_INITIALIZED) {
        return UART_PL011_ERR_NOT_INIT;
    }

    if(baudrate == 0) {
        return UART_PL011_ERR_INVALID_BAUD;
    }

    /* UART must be disabled before any Control Register or
    *  Line Control Register are reprogrammed */
    _uart_pl011_disable(p_uart);

    /* If baudrate is not valid ie UART_PL011_ERR_NONE is not returned then
     * the UART will continue to function at the old baudrate */
    err = _uart_pl011_set_baudrate(p_uart, dev->data->uart_clk, baudrate);

    if(err == UART_PL011_ERR_NONE) {
        dev->data->baudrate = baudrate;
    }

    if(uart_enabled) {
        _uart_pl011_enable(p_uart);
    }

    return err;
}

uint32_t uart_pl011_get_baudrate(struct uart_pl011_dev_t* dev)
{
    return dev->data->baudrate;
}

void uart_pl011_enable_intr(struct uart_pl011_dev_t* dev,
                    enum uart_pl011_intr_t mask)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    p_uart->uartimsc |= (uint32_t)(mask);

    return;
}

void uart_pl011_disable_intr(struct uart_pl011_dev_t* dev,
                    enum uart_pl011_intr_t mask)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    p_uart->uartimsc &= (uint32_t)(~mask);

    return;
}

void uart_pl011_clear_intr(struct uart_pl011_dev_t* dev,
                    enum uart_pl011_intr_t mask)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    p_uart->uarticr = (uint32_t)mask;

    return;
}


enum uart_pl011_intr_t uart_pl011_get_masked_intr_status(
                    struct uart_pl011_dev_t* dev)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    return (enum uart_pl011_intr_t)(p_uart->uartmis);

}

enum uart_pl011_intr_t uart_pl011_get_raw_intr_status(
                    struct uart_pl011_dev_t* dev)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    return (enum uart_pl011_intr_t)(p_uart->uartris);
}

void uart_pl011_set_rx_fifo_lvl(struct uart_pl011_dev_t* dev,
                    enum uart_pl011_rx_fifo_lvl_t rx_lvl)
{
    uint32_t fifo_lvl;

    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    /* Check if rx_lvl have valid values */
    rx_lvl &= UART_PL011_UARTIFLS_RX_FIFO_LVL_MASK;

    fifo_lvl = p_uart->uartifls
                        & ~(UART_PL011_UARTIFLS_RX_FIFO_LVL_MASK);
    p_uart->uartifls = fifo_lvl | rx_lvl;

    return;
}

void uart_pl011_set_tx_fifo_lvl(struct uart_pl011_dev_t* dev,
                    enum uart_pl011_tx_fifo_lvl_t tx_lvl)
{
    uint32_t fifo_lvl;

    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;
    /* Check if tx_lvl have valid values */
    tx_lvl &= UART_PL011_UARTIFLS_TX_FIFO_LVL_MASK;

    fifo_lvl = p_uart->uartifls
                        & ~(UART_PL011_UARTIFLS_TX_FIFO_LVL_MASK);
    p_uart->uartifls = fifo_lvl | tx_lvl;

    return;
}

void uart_pl011_set_tx_dma(struct uart_pl011_dev_t* dev,
                    enum uart_pl011_tx_dma_t enable)
{
    uint32_t dma_cr;

    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    enable &= UART_PL011_UARTDMACR_TX_MASK;

    dma_cr = p_uart->uartdmacr
                      & ~(UART_PL011_UARTDMACR_TX_MASK);

    p_uart->uartdmacr = dma_cr | enable;

    return;
}

void uart_pl011_set_rx_dma(struct uart_pl011_dev_t* dev,
                    enum uart_pl011_rx_dma_t enable)
{
    uint32_t dma_cr;

    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    enable &= UART_PL011_UARTDMACR_RX_MASK;

    dma_cr = p_uart->uartdmacr
                      & ~(UART_PL011_UARTDMACR_RX_MASK);

    p_uart->uartdmacr = dma_cr | enable;

    return;
}

bool uart_pl011_is_readable(struct uart_pl011_dev_t* dev)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    if( (uart_pl011_get_state(dev) == UART_PL011_INITIALIZED) &&
                /* UART is initialized */
        (p_uart->uartcr & UART_PL011_UARTCR_EN_MASK) &&
                /* UART is enabled */
        (p_uart->uartcr & UART_PL011_UARTCR_RX_EN_MASK) &&
                /* Receive is enabled */
        ((p_uart->uartfr & UART_PL011_UARTFR_RX_FIFO_EMPTY) == 0)) {
                /* Receive Fifo is not empty */
        return true;
    }

    return false;

}

enum uart_pl011_error_t uart_pl011_read(
                    struct uart_pl011_dev_t* dev, uint8_t* byte)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    *byte = p_uart->uartdr;

    return (enum uart_pl011_error_t)(p_uart->uartrsr
                                         & UART_PL011_RX_ERR_MASK);
}

bool uart_pl011_is_writable(struct uart_pl011_dev_t* dev)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    if( (uart_pl011_get_state(dev) == UART_PL011_INITIALIZED) &&
                /* UART is initialized */
        (p_uart->uartcr & UART_PL011_UARTCR_EN_MASK) &&
                /* UART is enabled */
        (p_uart->uartcr & UART_PL011_UARTCR_TX_EN_MASK) &&
                /* Transmit is enabled */
        ((p_uart->uartfr & UART_PL011_UARTFR_TX_FIFO_FULL) == 0)) {
                /* Transmit Fifo is not full */
        return true;
    }
    return false;

}

void uart_pl011_write(struct uart_pl011_dev_t* dev, uint8_t byte)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    p_uart->uartdr = byte;

    return;
}

enum uart_pl011_error_t uart_pl011_set_format(struct uart_pl011_dev_t* dev,
                    enum uart_pl011_wlen_t word_len,
                    enum uart_pl011_parity_t parity,
                    enum uart_pl011_stopbit_t stop_bits)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    bool uart_enabled = _uart_pl011_is_enabled(p_uart);

    if(uart_pl011_get_state(dev) != UART_PL011_INITIALIZED) {
        return UART_PL011_ERR_NOT_INIT;
    }

    /* UART must be disabled before any Control Register or
     * Line Control Register are reprogrammed */
    _uart_pl011_disable(p_uart);

    _uart_pl011_set_format(p_uart, word_len, parity, stop_bits);

    /* Enabling the UART if previously enabled */
    if(uart_enabled) {
        _uart_pl011_enable(p_uart);
    }

    return UART_PL011_ERR_NONE;
}

void uart_pl011_enable_fifo(struct uart_pl011_dev_t* dev)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    _uart_pl011_set_lcr_h_bit(p_uart, UART_PL011_UARTLCR_H_FEN_MASK);

    return;
}

void uart_pl011_disable_fifo(struct uart_pl011_dev_t* dev)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    _uart_pl011_clear_lcr_h_bit(p_uart, UART_PL011_UARTLCR_H_FEN_MASK);

    return;
}

void uart_pl011_enable_break(struct uart_pl011_dev_t* dev)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    _uart_pl011_set_lcr_h_bit(p_uart, UART_PL011_UARTLCR_H_BRK_MASK);

    return;
}

void uart_pl011_disable_break(struct uart_pl011_dev_t* dev)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    _uart_pl011_clear_lcr_h_bit(p_uart, UART_PL011_UARTLCR_H_BRK_MASK);

    return;
}

void uart_pl011_enable_cts_flowcontrol(struct uart_pl011_dev_t* dev)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    _uart_pl011_set_cr_bit(p_uart, UART_PL011_UARTCR_CTSE_MASK);

    return;
}

void uart_pl011_disable_cts_flowcontrol(struct uart_pl011_dev_t* dev)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    _uart_pl011_clear_cr_bit(p_uart, UART_PL011_UARTCR_CTSE_MASK);

    return;
}

void uart_pl011_enable_rts_flowcontrol(struct uart_pl011_dev_t* dev)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    _uart_pl011_set_cr_bit(p_uart, UART_PL011_UARTCR_RTSE_MASK);

    return;
}

void uart_pl011_disable_rts_flowcontrol(struct uart_pl011_dev_t* dev)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    _uart_pl011_clear_cr_bit(p_uart, UART_PL011_UARTCR_RTSE_MASK);

    return;
}

void uart_pl011_enable_ri(struct uart_pl011_dev_t* dev)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    _uart_pl011_set_cr_bit(p_uart, UART_PL011_UARTCR_OUT2_MASK);

    return;
}

void uart_pl011_disable_ri(struct uart_pl011_dev_t* dev)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    _uart_pl011_clear_cr_bit(p_uart, UART_PL011_UARTCR_OUT2_MASK);

    return;
}

void uart_pl011_enable_dcd(struct uart_pl011_dev_t* dev)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    _uart_pl011_set_cr_bit(p_uart, UART_PL011_UARTCR_OUT1_MASK);

    return;
}

void uart_pl011_disable_dcd(struct uart_pl011_dev_t* dev)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    _uart_pl011_clear_cr_bit(p_uart, UART_PL011_UARTCR_OUT1_MASK);

    return;
}

void uart_pl011_set_rts(struct uart_pl011_dev_t* dev)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    _uart_pl011_set_cr_bit(p_uart, UART_PL011_UARTCR_RTS_MASK);

    return;
}

void uart_pl011_clear_rts(struct uart_pl011_dev_t* dev)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    _uart_pl011_clear_cr_bit(p_uart, UART_PL011_UARTCR_RTS_MASK);

    return;
}

void uart_pl011_set_dtr(struct uart_pl011_dev_t* dev)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    _uart_pl011_set_cr_bit(p_uart, UART_PL011_UARTCR_DTR_MASK);

    return;
}

void uart_pl011_clear_dtr(struct uart_pl011_dev_t* dev)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    _uart_pl011_clear_cr_bit(p_uart, UART_PL011_UARTCR_DTR_MASK);

    return;
}

void uart_pl011_enable_receive(struct uart_pl011_dev_t* dev)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    _uart_pl011_set_cr_bit(p_uart, UART_PL011_UARTCR_RX_EN_MASK);

    return;
}

void uart_pl011_disable_receive(struct uart_pl011_dev_t* dev)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    _uart_pl011_clear_cr_bit(p_uart, UART_PL011_UARTCR_RX_EN_MASK);

    return;
}

void uart_pl011_enable_transmit(struct uart_pl011_dev_t* dev)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    _uart_pl011_set_cr_bit(p_uart, UART_PL011_UARTCR_TX_EN_MASK);

    return;
}

void uart_pl011_disable_transmit(struct uart_pl011_dev_t* dev)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    _uart_pl011_clear_cr_bit(p_uart, UART_PL011_UARTCR_TX_EN_MASK);

    return;
}

void uart_pl011_set_loopback(struct uart_pl011_dev_t* dev)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    _uart_pl011_set_cr_bit(p_uart, UART_PL011_UARTCR_LBE_MASK);

    return;
}

void uart_pl011_clear_loopback(struct uart_pl011_dev_t* dev)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    _uart_pl011_clear_cr_bit(p_uart, UART_PL011_UARTCR_LBE_MASK);

    return;
}

void uart_pl011_enable_sirlp(struct uart_pl011_dev_t* dev)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    _uart_pl011_set_cr_bit(p_uart,
     UART_PL011_UARTCR_SIREN_MASK | UART_PL011_UARTCR_SIRLP_MASK);

    return;
}

void uart_pl011_disable_sirlp(struct uart_pl011_dev_t* dev)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    _uart_pl011_clear_cr_bit(p_uart,
     UART_PL011_UARTCR_SIREN_MASK | UART_PL011_UARTCR_SIRLP_MASK);

    return;
}

void uart_pl011_enable_sir(struct uart_pl011_dev_t* dev)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    _uart_pl011_set_cr_bit(p_uart, UART_PL011_UARTCR_SIREN_MASK);

    return;
}

void uart_pl011_disable_sir(struct uart_pl011_dev_t* dev)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    _uart_pl011_clear_cr_bit(p_uart, UART_PL011_UARTCR_SIREN_MASK);

    return;
}

void uart_pl011_enable(struct uart_pl011_dev_t* dev)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    _uart_pl011_enable(p_uart);

    return;
}

void uart_pl011_disable(struct uart_pl011_dev_t* dev)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    _uart_pl011_disable(p_uart);

    return;
}

bool uart_pl011_get_cts_status(struct uart_pl011_dev_t* dev)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;
    return (bool)(p_uart->uartfr & UART_PL011_UARTFR_CTS_MASK);

}

bool uart_pl011_get_dsr_status(struct uart_pl011_dev_t* dev)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;
    return (bool)(p_uart->uartfr & UART_PL011_UARTFR_DSR_MASK);

}

bool uart_pl011_get_dcd_status(struct uart_pl011_dev_t* dev)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;
    return (bool)(p_uart->uartfr & UART_PL011_UARTFR_DCD_MASK);

}

bool uart_pl011_get_ri_status(struct uart_pl011_dev_t* dev)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;
    return (bool)(p_uart->uartfr & UART_PL011_UARTFR_RI_MASK);

}

enum uart_pl011_error_t uart_pl011_set_sirlp_divisor(
            struct uart_pl011_dev_t* dev, uint32_t value)
{
    struct _uart_pl011_reg_map_t* p_uart =
        (struct _uart_pl011_reg_map_t*)dev->cfg->base;

    uint32_t irlp_baud16_clk;

    if(uart_pl011_get_state(dev) != UART_PL011_INITIALIZED) {
        return UART_PL011_ERR_NOT_INIT;
    }

    if(value == 0) {
        return UART_PL011_ERR_INVALID_ARG;
    }

    irlp_baud16_clk = dev->data->uart_clk/value;

    /* Chose the divisor so that 1.42MHz < FIrLPBaud16 < 2.12MHz, that
     * results in a low-power pulse duration of 1.41–2.11μs (three times
     * the period of IrLPBaud16). ARM DDI0183F Pg 3-9 */
    if(irlp_baud16_clk < FREQ_IRLPBAUD16_MIN ||
       irlp_baud16_clk > FREQ_IRLPBAUD16_MAX) {
        return UART_PL011_ERR_INVALID_ARG;
    }

    p_uart->uartilpr = value;

    return UART_PL011_ERR_NONE;
}