diff options
Diffstat (limited to 'platform')
-rw-r--r-- | platform/ext/target/mps2/an539/spm_hal.c | 209 | ||||
-rw-r--r-- | platform/ext/target/mps2/an539/target_cfg.c | 575 | ||||
-rw-r--r-- | platform/ext/target/mps2/an539/target_cfg.h | 172 | ||||
-rw-r--r-- | platform/ext/target/mps2/an539/tfm_peripherals_def.h | 35 |
4 files changed, 0 insertions, 991 deletions
diff --git a/platform/ext/target/mps2/an539/spm_hal.c b/platform/ext/target/mps2/an539/spm_hal.c deleted file mode 100644 index 0f967684f0..0000000000 --- a/platform/ext/target/mps2/an539/spm_hal.c +++ /dev/null @@ -1,209 +0,0 @@ -/* - * Copyright (c) 2019-2020, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include <stdio.h> -#include "tfm_spm_hal.h" -#include "tfm_platform_core_api.h" -#include "target_cfg.h" -#include "mpu_armv8m_drv.h" -#include "region_defs.h" -#include "platform_description.h" -#include "region.h" -#include "tfm_hal_platform.h" -#include "interface/include/log/tfm_log.h" - -/* Debug configuration flags */ -#define SPNIDEN_SEL_STATUS (0x01u << 7) -#define SPNIDEN_STATUS (0x01u << 6) -#define SPIDEN_SEL_STATUS (0x01u << 5) -#define SPIDEN_STATUS (0x01u << 4) -#define NIDEN_SEL_STATUS (0x01u << 3) -#define NIDEN_STATUS (0x01u << 2) -#define DBGEN_SEL_STATUS (0x01u << 1) -#define DBGEN_STATUS (0x01u << 0) - -#define All_SEL_STATUS (SPNIDEN_SEL_STATUS | SPIDEN_SEL_STATUS | \ - NIDEN_SEL_STATUS | DBGEN_SEL_STATUS) - -/* Get address of memory regions to configure MPU */ -extern const struct memory_region_limits memory_regions; - -enum tfm_plat_err_t tfm_spm_hal_configure_default_isolation( - uint32_t partition_idx, - const struct platform_data_t *platform_data) -{ - bool privileged = tfm_is_partition_privileged(partition_idx); - - if (!platform_data) { - return TFM_PLAT_ERR_INVALID_INPUT; - } - - if (platform_data->periph_ppc_bank != PPC_SP_DO_NOT_CONFIGURE) { - ppc_configure_to_secure(platform_data->periph_ppc_bank, - platform_data->periph_ppc_loc); - if (privileged) { - ppc_configure_to_secure_priv(platform_data->periph_ppc_bank, - platform_data->periph_ppc_loc); - } else { - ppc_configure_to_secure_unpriv(platform_data->periph_ppc_bank, - platform_data->periph_ppc_loc); - } - } - return TFM_PLAT_ERR_SUCCESS; -} - -void MPC_Handler(void) -{ - /* Clear MPC interrupt flag and pending MPC IRQ */ - mpc_clear_irq(); - NVIC_ClearPendingIRQ(MPC_IRQn); - - /* Print fault message and block execution */ - ERROR_MSG("Oops... MPC fault!!!"); - - /* Inform TF-M core that isolation boundary has been violated */ - tfm_access_violation_handler(); -} - -void PPC_Handler(void) -{ - /* Clear PPC interrupt flag and pending PPC IRQ */ - ppc_clear_irq(); - NVIC_ClearPendingIRQ(PPC_IRQn); - - /* Print fault message*/ - ERROR_MSG("Oops... PPC fault!!!"); - - /* Inform TF-M core that isolation boundary has been violated */ - tfm_access_violation_handler(); -} - -uint32_t tfm_spm_hal_get_ns_VTOR(void) -{ - return memory_regions.non_secure_code_start; -} - -uint32_t tfm_spm_hal_get_ns_MSP(void) -{ - return *((uint32_t *)memory_regions.non_secure_code_start); -} - -uint32_t tfm_spm_hal_get_ns_entry_point(void) -{ - return *((uint32_t *)(memory_regions.non_secure_code_start + 4)); -} - -enum tfm_plat_err_t tfm_spm_hal_set_secure_irq_priority(IRQn_Type irq_line, uint32_t priority) -{ - uint32_t quantized_priority = priority >> (8U - __NVIC_PRIO_BITS); - NVIC_SetPriority(irq_line, quantized_priority); - - return TFM_PLAT_ERR_SUCCESS; -} - -enum tfm_plat_err_t tfm_spm_hal_init_debug(void) -{ - volatile struct sse123_sysctrl_t *sys_ctrl = - (struct sse123_sysctrl_t *)SSE123_SYSCTRL_BASE_S; - -#if defined(DAUTH_NONE) - /* Set all the debug enable selector bits to 1 */ - sys_ctrl->secdbgset = All_SEL_STATUS; - /* Set all the debug enable bits to 0 */ - sys_ctrl->secdbgclr = - DBGEN_STATUS | NIDEN_STATUS | SPIDEN_STATUS | SPNIDEN_STATUS; -#elif defined(DAUTH_NS_ONLY) - /* Set all the debug enable selector bits to 1 */ - sys_ctrl->secdbgset = All_SEL_STATUS; - /* Set the debug enable bits to 1 for NS, and 0 for S mode */ - sys_ctrl->secdbgset = DBGEN_STATUS | NIDEN_STATUS; - sys_ctrl->secdbgclr = SPIDEN_STATUS | SPNIDEN_STATUS; -#elif defined(DAUTH_FULL) - /* Set all the debug enable selector bits to 1 */ - sys_ctrl->secdbgset = All_SEL_STATUS; - /* Set all the debug enable bits to 1 */ - sys_ctrl->secdbgset = - DBGEN_STATUS | NIDEN_STATUS | SPIDEN_STATUS | SPNIDEN_STATUS; -#else - -#if !defined(DAUTH_CHIP_DEFAULT) -#error "No debug authentication setting is provided." -#endif - - /* Set all the debug enable selector bits to 0 */ - sys_ctrl->secdbgclr = All_SEL_STATUS; - - /* No need to set any enable bits because the value depends on - * input signals. - */ -#endif - - return TFM_PLAT_ERR_SUCCESS; -} - -enum irq_target_state_t tfm_spm_hal_set_irq_target_state( - IRQn_Type irq_line, - enum irq_target_state_t target_state) -{ - uint32_t result; - - if (target_state == TFM_IRQ_TARGET_STATE_SECURE) { - result = NVIC_ClearTargetState(irq_line); - } else { - result = NVIC_SetTargetState(irq_line); - } - - if (result) { - return TFM_IRQ_TARGET_STATE_NON_SECURE; - } else { - return TFM_IRQ_TARGET_STATE_SECURE; - } -} - -enum tfm_plat_err_t tfm_spm_hal_enable_fault_handlers(void) -{ - return enable_fault_handlers(); -} - -enum tfm_plat_err_t tfm_spm_hal_system_reset_cfg(void) -{ - return system_reset_cfg(); -} - -enum tfm_plat_err_t tfm_spm_hal_nvic_interrupt_target_state_cfg(void) -{ - return nvic_interrupt_target_state_cfg(); -} - -enum tfm_plat_err_t tfm_spm_hal_nvic_interrupt_enable(void) -{ - return nvic_interrupt_enable(); -} - -void tfm_spm_hal_clear_pending_irq(IRQn_Type irq_line) -{ - NVIC_ClearPendingIRQ(irq_line); -} - -void tfm_spm_hal_enable_irq(IRQn_Type irq_line) -{ - NVIC_EnableIRQ(irq_line); -} - -void tfm_spm_hal_disable_irq(IRQn_Type irq_line) -{ - NVIC_DisableIRQ(irq_line); -} - -enum tfm_hal_status_t tfm_hal_platform_init(void) -{ - __enable_irq(); - stdio_init(); - LOG_MSG("\033[1;34m[Platform] AN539 is marked for deprecation!\033[0m\r\n"); - - return TFM_HAL_SUCCESS; -} diff --git a/platform/ext/target/mps2/an539/target_cfg.c b/platform/ext/target/mps2/an539/target_cfg.c deleted file mode 100644 index 9a2b2a1faa..0000000000 --- a/platform/ext/target/mps2/an539/target_cfg.c +++ /dev/null @@ -1,575 +0,0 @@ -/* - * Copyright (c) 2019-2020 Arm Limited. All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_cfg.h" -#include "Driver_MPC.h" -#include "Driver_SSE123_PPC.h" -#include "device_definition.h" -#include "platform_description.h" -#include "region_defs.h" -#include "utilities.h" -#include "mpu_armv8m_drv.h" -#include "tfm_plat_defs.h" -#include "region.h" - -/* Throw out bus error when an access causes security violation */ -#define CMSDK_SECRESPCFG_BUS_ERR_MASK (1UL << 0) - -/* The section names come from the scatter file */ -REGION_DECLARE(Load$$LR$$, LR_NS_PARTITION, $$Base); -REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Base); -REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Limit); -#ifdef BL2 -REGION_DECLARE(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base); -#endif /* BL2 */ - -const struct memory_region_limits memory_regions = { - .non_secure_code_start = - (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) + - BL2_HEADER_SIZE, - - .non_secure_partition_base = - (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base), - - .non_secure_partition_limit = - (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) + - NS_PARTITION_SIZE - 1, - - .veneer_base = - (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Base), - - .veneer_limit = - (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Limit), - -#ifdef BL2 - .secondary_partition_base = - (uint32_t)®ION_NAME(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base), - - .secondary_partition_limit = - (uint32_t)®ION_NAME(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base) + - SECONDARY_PARTITION_SIZE - 1, -#endif /* BL2 */ -}; - -static struct mpu_armv8m_dev_t dev_mpu = { MPU_BASE }; - -/* Allows software, via SAU, to define the code region as a NSC */ -#define NSCCFG_CODENSC 1 - -/* Import MPC drivers */ -extern ARM_DRIVER_MPC Driver_ISRAM0_MPC; -extern ARM_DRIVER_MPC Driver_SRAM1_MPC; -extern ARM_DRIVER_MPC Driver_SRAM2_MPC; -extern ARM_DRIVER_MPC Driver_SSRAM3_MPC; - -/* Import PPC drivers */ -extern DRIVER_PPC_SSE123 Driver_PPC_SSE123_AHB_EXP0; -extern DRIVER_PPC_SSE123 Driver_PPC_SSE123_APB; -extern DRIVER_PPC_SSE123 Driver_PPC_SSE123_APB_EXP0; -extern DRIVER_PPC_SSE123 Driver_PPC_SSE123_APB_EXP1; -extern DRIVER_PPC_SSE123 Driver_PPC_SSE123_APB_EXP2; -extern DRIVER_PPC_SSE123 Driver_PPC_SSE123_APB_EXP3; - -/* Define Peripherals NS address range for the platform */ -#define PERIPHERALS_BASE_NS_START (0x40000000) -#define PERIPHERALS_BASE_NS_END (0x4FFFFFFF) - -/* Enable system reset request for CPU 0 */ -#define ENABLE_CPU0_SYSTEM_RESET_REQUEST (1U << 4U) - -/* To write into AIRCR register, 0x5FA value must be write to the VECTKEY field, - * otherwise the processor ignores the write. - */ -#define SCB_AIRCR_WRITE_MASK ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)) - -struct platform_data_t tfm_peripheral_std_uart = { - UART0_BASE_NS, - UART0_BASE_NS + 0xFFF, - PPC_SP_DO_NOT_CONFIGURE, - -1 -}; - -struct platform_data_t tfm_peripheral_fpga_io = { - MPS2_IO_FPGAIO_BASE_S, - MPS2_IO_FPGAIO_BASE_S + 0xFFF, - PPC_SP_APB_PPC_EXP3, - FPGA_IO_APB_PPCEXP3_POS -}; - -struct platform_data_t tfm_peripheral_timer0 = { - SYSTEM_TIMER0_BASE_S, - SYSTEM_TIMER1_BASE_S - 1, - PPC_SP_APB_PPC, - SYSTEM_TIMER0_APB_PPC_POS -}; - -static DRIVER_PPC_SSE123 *const ppc_bank_drivers[] = { - &Driver_PPC_SSE123_AHB_EXP0, /* AHB PPCEXP0 */ - &Driver_PPC_SSE123_APB, /* APB PPC0 */ - &Driver_PPC_SSE123_APB_EXP0, /* APB PPCEXP0 */ - &Driver_PPC_SSE123_APB_EXP1, /* APB PPCEXP1 */ - &Driver_PPC_SSE123_APB_EXP2, /* APB PPCEXP2 */ - &Driver_PPC_SSE123_APB_EXP3, /* APB PPCEXP3 */ -}; - -#define PPC_BANK_COUNT (sizeof(ppc_bank_drivers)/sizeof(ppc_bank_drivers[0])) - -enum tfm_plat_err_t enable_fault_handlers(void) -{ - /* Secure fault is not present in the Baseline implementation. */ - /* Fault handler enable registers are not present in a Baseline - * implementation. - */ - - return TFM_PLAT_ERR_SUCCESS; -} - -enum tfm_plat_err_t system_reset_cfg(void) -{ - struct sse123_sysctrl_t *sysctrl = - (struct sse123_sysctrl_t *)SSE123_SYSCTRL_BASE_S; - uint32_t reg_value = SCB->AIRCR; - - /* Enable system reset request for CPU 0, to be triggered via - * NVIC_SystemReset function. - */ - sysctrl->resetmask |= ENABLE_CPU0_SYSTEM_RESET_REQUEST; - - /* Clear SCB_AIRCR_VECTKEY value */ - reg_value &= ~(uint32_t)(SCB_AIRCR_VECTKEY_Msk); - - /* Enable system reset request only to the secure world */ - reg_value |= (uint32_t)(SCB_AIRCR_WRITE_MASK | SCB_AIRCR_SYSRESETREQS_Msk); - - SCB->AIRCR = reg_value; - - return TFM_PLAT_ERR_SUCCESS; -} - -/*--------------------- NVIC interrupt NS/S configuration --------------------*/ -enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void) -{ - uint8_t i; - - /* Target every interrupt to NS; unimplemented interrupts will be WI */ - for (i = 0; i < (sizeof(NVIC->ITNS) / sizeof(NVIC->ITNS[0])); i++) { - NVIC->ITNS[i] = 0xFFFFFFFF; - } - - /* Make sure that MPC and PPC are targeted to S state */ - NVIC_ClearTargetState(MPC_IRQn); - NVIC_ClearTargetState(PPC_IRQn); - - return TFM_PLAT_ERR_SUCCESS; -} - -enum mpu_armv8m_error_t mpu_enable(uint32_t privdef_en, uint32_t hfnmi_en) -{ - return mpu_armv8m_enable(&dev_mpu, privdef_en, hfnmi_en); -} - -enum mpu_armv8m_error_t mpu_disable(void) -{ - return mpu_armv8m_disable(&dev_mpu); -} - -enum mpu_armv8m_error_t mpu_region_enable( - struct mpu_armv8m_region_cfg_t *region_cfg) -{ - if (!region_cfg) { - return MPU_ARMV8M_ERROR; - } - - return mpu_armv8m_region_enable(&dev_mpu, region_cfg); -} - -enum mpu_armv8m_error_t mpu_region_disable(uint32_t region_nr) -{ - return mpu_armv8m_region_disable(&dev_mpu, region_nr); -} - -enum mpu_armv8m_error_t mpu_clean(void) -{ - return mpu_armv8m_clean(&dev_mpu); -} - -/*----------------- NVIC interrupt enabling for S peripherals ----------------*/ -enum tfm_plat_err_t nvic_interrupt_enable(void) -{ - int32_t ret = ARM_DRIVER_OK; - - /* MPC interrupt enabling */ - mpc_clear_irq(); - ret = Driver_SRAM1_MPC.EnableInterrupt(); - if (ret != ARM_DRIVER_OK) { - ERROR_MSG("Failed to Enable MPC interrupt for SSRAM1!"); - return TFM_PLAT_ERR_SYSTEM_ERR; - } - ret = Driver_SRAM2_MPC.EnableInterrupt(); - if (ret != ARM_DRIVER_OK) { - ERROR_MSG("Failed to Enable MPC interrupt for SSRAM2!"); - return TFM_PLAT_ERR_SYSTEM_ERR; - } - NVIC_ClearPendingIRQ(MPC_IRQn); - NVIC_EnableIRQ(MPC_IRQn); - - /* PPC interrupt enabling */ - /* Clear pending PPC interrupts */ - /* In the PPC configuration function, we have used the Non-Secure - * Privilege Control Block to grant unprivilged NS access to some - * peripherals used by NS. That triggers a PPC0 exception as that - * register is meant for NS privileged access only. Clear it here - */ - NVIC_ClearPendingIRQ(PPC_IRQn); - Driver_PPC_SSE123_APB.ClearInterrupt(); - - /* Enable PPC interrupts for APB PPC */ - ret = Driver_PPC_SSE123_APB.EnableInterrupt(); - if (ret != ARM_DRIVER_OK) { - ERROR_MSG("Failed to Enable PPC APB interrupt!"); - return TFM_PLAT_ERR_SYSTEM_ERR; - } - - ret = Driver_PPC_SSE123_APB_EXP2.EnableInterrupt(); - if (ret != ARM_DRIVER_OK) { - ERROR_MSG("Failed to Enable PPC APB EXP2 interrupt!"); - return TFM_PLAT_ERR_SYSTEM_ERR; - } - - ret = Driver_PPC_SSE123_APB_EXP3.EnableInterrupt(); - if (ret != ARM_DRIVER_OK) { - ERROR_MSG("Failed to Enable PPC APB EXP3 interrupt!"); - return TFM_PLAT_ERR_SYSTEM_ERR; - } - - NVIC_EnableIRQ(PPC_IRQn); - - return TFM_PLAT_ERR_SUCCESS; -} - -/*------------------- SAU/IDAU configuration functions -----------------------*/ -void sau_and_idau_cfg(void) -{ - struct sse123_spctrl_t *spctrl = (struct sse123_spctrl_t*)SSE123_SPCTRL_BASE_S; - - /* Enables SAU */ - TZ_SAU_Enable(); - - /* Configures SAU regions to be non-secure */ - SAU->RNR = 0U; - SAU->RBAR = (memory_regions.non_secure_partition_base - & SAU_RBAR_BADDR_Msk); - SAU->RLAR = (memory_regions.non_secure_partition_limit - & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk; - - SAU->RNR = 1U; - SAU->RBAR = (NS_DATA_START & SAU_RBAR_BADDR_Msk); - SAU->RLAR = (NS_DATA_LIMIT & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk; - - /* Configures veneers region to be non-secure callable */ - SAU->RNR = 2U; - SAU->RBAR = (memory_regions.veneer_base & SAU_RBAR_BADDR_Msk); - SAU->RLAR = (memory_regions.veneer_limit & SAU_RLAR_LADDR_Msk) - | SAU_RLAR_ENABLE_Msk | SAU_RLAR_NSC_Msk; - - /* Configure the peripherals space */ - SAU->RNR = 3U; - SAU->RBAR = (PERIPHERALS_BASE_NS_START & SAU_RBAR_BADDR_Msk); - SAU->RLAR = (PERIPHERALS_BASE_NS_END & SAU_RLAR_LADDR_Msk) - | SAU_RLAR_ENABLE_Msk; -#ifdef BL2 - /* Secondary image partition */ - SAU->RNR = 4U; - SAU->RBAR = (memory_regions.secondary_partition_base - & SAU_RBAR_BADDR_Msk); - SAU->RLAR = (memory_regions.secondary_partition_limit - & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk; -#endif /* BL2 */ - - /* Allows SAU to define the code region as a NSC */ - spctrl->nsccfg |= NSCCFG_CODENSC; -} - -/*------------------- Memory configuration functions -------------------------*/ -enum tfm_plat_err_t mpc_init_cfg(void) -{ - int32_t ret = ARM_DRIVER_OK; - - ret = Driver_SRAM1_MPC.Initialize(); - if (ret != ARM_DRIVER_OK) { - ERROR_MSG("Failed to Initialize MPC for SSRAM1!"); - return TFM_PLAT_ERR_SYSTEM_ERR; - } - ret = Driver_SRAM1_MPC.ConfigRegion( - memory_regions.non_secure_partition_base, - memory_regions.non_secure_partition_limit, - ARM_MPC_ATTR_NONSECURE); - if (ret != ARM_DRIVER_OK) { - ERROR_MSG("Failed to Configure MPC for SSRAM1!"); - return TFM_PLAT_ERR_SYSTEM_ERR; - } - -#ifdef BL2 - ret = Driver_SRAM1_MPC.ConfigRegion( - memory_regions.secondary_partition_base, - memory_regions.secondary_partition_limit, - ARM_MPC_ATTR_NONSECURE); - if (ret != ARM_DRIVER_OK) { - ERROR_MSG("Failed to Configure MPC for SSRAM1!"); - return TFM_PLAT_ERR_SYSTEM_ERR; - } -#endif - - ret = Driver_SRAM2_MPC.Initialize(); - if (ret != ARM_DRIVER_OK) { - ERROR_MSG("Failed to Initialize MPC for SSRAM2!"); - return TFM_PLAT_ERR_SYSTEM_ERR; - } - ret = Driver_SRAM2_MPC.ConfigRegion(NS_DATA_START, NS_DATA_LIMIT, - ARM_MPC_ATTR_NONSECURE); - if (ret != ARM_DRIVER_OK) { - ERROR_MSG("Failed to Configure MPC for SSRAM2!"); - return TFM_PLAT_ERR_SYSTEM_ERR; - } - - /* Lock down the MPC configuration */ - ret = Driver_SRAM1_MPC.LockDown(); - if (ret != ARM_DRIVER_OK) { - ERROR_MSG("Failed to Lock down MPC for SSRAM1!"); - return TFM_PLAT_ERR_SYSTEM_ERR; - } - ret = Driver_SRAM2_MPC.LockDown(); - if (ret != ARM_DRIVER_OK) { - ERROR_MSG("Failed to Lock down MPC for SSRAM2!"); - return TFM_PLAT_ERR_SYSTEM_ERR; - } - - /* Initialize and lock down not used MPC drivers. */ - ret = Driver_ISRAM0_MPC.Initialize(); - if (ret != ARM_DRIVER_OK) { - ERROR_MSG("Failed to Initialize MPC for ISRAM0!"); - return TFM_PLAT_ERR_SYSTEM_ERR; - } - ret = Driver_SSRAM3_MPC.Initialize(); - if (ret != ARM_DRIVER_OK) { - ERROR_MSG("Failed to Initialize MPC for SSRAM3!"); - return TFM_PLAT_ERR_SYSTEM_ERR; - } - - ret = Driver_ISRAM0_MPC.LockDown(); - if (ret != ARM_DRIVER_OK) { - ERROR_MSG("Failed to Lock down MPC for ISRAM0!"); - return TFM_PLAT_ERR_SYSTEM_ERR; - } - ret = Driver_SSRAM3_MPC.LockDown(); - if (ret != ARM_DRIVER_OK) { - ERROR_MSG("Failed to Lock down MPC for SSRAM3!"); - return TFM_PLAT_ERR_SYSTEM_ERR; - } - - /* Add barriers to assure the MPC configuration is done before continue - * the execution. - */ - __DSB(); - __ISB(); - - return TFM_PLAT_ERR_SUCCESS; -} - -void mpc_clear_irq(void) -{ - Driver_SRAM1_MPC.ClearInterrupt(); - Driver_SRAM2_MPC.ClearInterrupt(); -} - -/*------------------- PPC configuration functions -------------------------*/ -enum tfm_plat_err_t ppc_init_cfg(void) -{ - struct sse123_spctrl_t *spctrl = - (struct sse123_spctrl_t*)SSE123_SPCTRL_BASE_S; - int32_t err = ARM_DRIVER_OK; - - /* Grant non-secure access to peripherals in the PPC0 - * (timer0 and 1, dualtimer, watchdog, mhu 0 and 1) - */ - err |= Driver_PPC_SSE123_APB.Initialize(); - err |= Driver_PPC_SSE123_APB.ConfigSecurity(SYSTEM_TIMER0_APB_PPC_POS, - PPC_SSE123_NONSECURE_CONFIG); - err |= Driver_PPC_SSE123_APB.ConfigSecurity(SYSTEM_TIMER1_APB_PPC_POS, - PPC_SSE123_NONSECURE_CONFIG); - err |= Driver_PPC_SSE123_APB.ConfigSecurity(SYSTEM_WATCHDOG_APB_PPC_POS, - PPC_SSE123_NONSECURE_CONFIG); - - /* Grant non-secure access for APB peripherals on EXP2 */ - err |= Driver_PPC_SSE123_APB_EXP2.Initialize(); - err |= Driver_PPC_SSE123_APB_EXP2.ConfigSecurity(SPI0_APB_PPCEXP2_POS, - PPC_SSE123_NONSECURE_CONFIG); - err |= Driver_PPC_SSE123_APB_EXP2.ConfigSecurity(SPI1_APB_PPCEXP2_POS, - PPC_SSE123_NONSECURE_CONFIG); - err |= Driver_PPC_SSE123_APB_EXP2.ConfigSecurity(SPI2_APB_PPCEXP2_POS, - PPC_SSE123_NONSECURE_CONFIG); - err |= Driver_PPC_SSE123_APB_EXP2.ConfigSecurity(SPI3_APB_PPCEXP2_POS, - PPC_SSE123_NONSECURE_CONFIG); - err |= Driver_PPC_SSE123_APB_EXP2.ConfigSecurity(SPI4_APB_PPCEXP2_POS, - PPC_SSE123_NONSECURE_CONFIG); - err |= Driver_PPC_SSE123_APB_EXP2.ConfigSecurity(UART0_APB_PPCEXP2_POS, - PPC_SSE123_NONSECURE_CONFIG); - err |= Driver_PPC_SSE123_APB_EXP2.ConfigSecurity(UART1_APB_PPCEXP2_POS, - PPC_SSE123_NONSECURE_CONFIG); - err |= Driver_PPC_SSE123_APB_EXP2.ConfigSecurity(UART2_APB_PPCEXP2_POS, - PPC_SSE123_NONSECURE_CONFIG); - err |= Driver_PPC_SSE123_APB_EXP2.ConfigSecurity(UART3_APB_PPCEXP2_POS, - PPC_SSE123_NONSECURE_CONFIG); - err |= Driver_PPC_SSE123_APB_EXP2.ConfigSecurity(UART4_APB_PPCEXP2_POS, - PPC_SSE123_NONSECURE_CONFIG); - err |= Driver_PPC_SSE123_APB_EXP2.ConfigSecurity(I2C0_APB_PPCEXP2_POS, - PPC_SSE123_NONSECURE_CONFIG); - err |= Driver_PPC_SSE123_APB_EXP2.ConfigSecurity(I2C1_APB_PPCEXP2_POS, - PPC_SSE123_NONSECURE_CONFIG); - err |= Driver_PPC_SSE123_APB_EXP2.ConfigSecurity(I2C2_APB_PPCEXP2_POS, - PPC_SSE123_NONSECURE_CONFIG); - err |= Driver_PPC_SSE123_APB_EXP2.ConfigSecurity(I2C3_APB_PPCEXP2_POS, - PPC_SSE123_NONSECURE_CONFIG); - - /* Grant un-privileged access for UART0 in NS domain */ - err |= Driver_PPC_SSE123_APB_EXP2.ConfigPrivilege(UART0_APB_PPCEXP2_POS, - PPC_SSE123_NONSECURE_CONFIG, - PPC_SSE123_PRIV_AND_NONPRIV_CONFIG); - - /* Grant non-secure access for APB peripherals on EXP3 */ - err |= Driver_PPC_SSE123_APB_EXP3.Initialize(); - err |= Driver_PPC_SSE123_APB_EXP3.ConfigSecurity(FPGA_SCC_APB_PPCEXP3_POS, - PPC_SSE123_NONSECURE_CONFIG); - - err |= Driver_PPC_SSE123_APB_EXP3.ConfigSecurity(FPGA_AUDIO_APB_PPCEXP3_POS, - PPC_SSE123_NONSECURE_CONFIG); - - err |= Driver_PPC_SSE123_APB_EXP3.ConfigSecurity(FPGA_IO_APB_PPCEXP3_POS, - PPC_SSE123_NONSECURE_CONFIG); - - /* Grant un-privileged access for LEDs in NS domain */ - err |= Driver_PPC_SSE123_APB_EXP3.ConfigPrivilege(FPGA_SCC_APB_PPCEXP3_POS, - PPC_SSE123_NONSECURE_CONFIG, - PPC_SSE123_PRIV_AND_NONPRIV_CONFIG); - - err |= Driver_PPC_SSE123_APB_EXP3.ConfigPrivilege(FPGA_IO_APB_PPCEXP3_POS, - PPC_SSE123_NONSECURE_CONFIG, - PPC_SSE123_PRIV_AND_NONPRIV_CONFIG); - - /* - * Grant non-secure access to all peripherals on AHB EXP0: - * Make sure that all possible peripherals are enabled by default - */ - err |= Driver_PPC_SSE123_AHB_EXP0.Initialize(); - err |= Driver_PPC_SSE123_AHB_EXP0.ConfigSecurity(VGA_AHB_PPCEXP_POS, - PPC_SSE123_NONSECURE_CONFIG); - err |= Driver_PPC_SSE123_AHB_EXP0.ConfigSecurity(GPIO0_AHB_PPCEXP_POS, - PPC_SSE123_NONSECURE_CONFIG); - err |= Driver_PPC_SSE123_AHB_EXP0.ConfigSecurity(GPIO1_AHB_PPCEXP_POS, - PPC_SSE123_NONSECURE_CONFIG); - err |= Driver_PPC_SSE123_AHB_EXP0.ConfigSecurity(GPIO2_AHB_PPCEXP_POS, - PPC_SSE123_NONSECURE_CONFIG); - err |= Driver_PPC_SSE123_AHB_EXP0.ConfigSecurity(GPIO3_AHB_PPCEXP_POS, - PPC_SSE123_NONSECURE_CONFIG); - err |= Driver_PPC_SSE123_AHB_EXP0.ConfigSecurity(PSRAM_ETH_AHB_PPCEXP_POS, - PPC_SSE123_NONSECURE_CONFIG); - err |= Driver_PPC_SSE123_AHB_EXP0.ConfigSecurity(DMA0_AHB_PPCEXP_POS, - PPC_SSE123_NONSECURE_CONFIG); - err |= Driver_PPC_SSE123_AHB_EXP0.ConfigSecurity(DMA1_AHB_PPCEXP_POS, - PPC_SSE123_NONSECURE_CONFIG); - - /* Initialize not used PPC drivers */ - err |= Driver_PPC_SSE123_APB_EXP0.Initialize(); - err |= Driver_PPC_SSE123_APB_EXP1.Initialize(); - - /* - * Configure the response to a security violation as a - * bus error instead of RAZ/WI - */ - spctrl->secrespcfg |= CMSDK_SECRESPCFG_BUS_ERR_MASK; - - if (err != ARM_DRIVER_OK) { - return TFM_PLAT_ERR_SYSTEM_ERR; - } - - return TFM_PLAT_ERR_SUCCESS; -} - -void ppc_configure_to_secure(enum ppc_bank_e bank, uint32_t pos) -{ - DRIVER_PPC_SSE123 *ppc_driver; - - if (bank >= PPC_BANK_COUNT) { - return; - } - - ppc_driver = ppc_bank_drivers[bank]; - if (ppc_driver) { - ppc_driver->ConfigSecurity(pos, PPC_SSE123_SECURE_CONFIG); - } -} - -void ppc_configure_to_non_secure(enum ppc_bank_e bank, uint32_t pos) -{ - DRIVER_PPC_SSE123 *ppc_driver; - - if (bank >= PPC_BANK_COUNT) { - return; - } - - ppc_driver = ppc_bank_drivers[bank]; - if (ppc_driver) { - ppc_driver->ConfigSecurity(pos, PPC_SSE123_NONSECURE_CONFIG); - } -} - -void ppc_configure_to_secure_priv(enum ppc_bank_e bank, uint32_t pos) -{ - DRIVER_PPC_SSE123 *ppc_driver; - - if (bank >= PPC_BANK_COUNT) { - return; - } - - ppc_driver = ppc_bank_drivers[bank]; - if (ppc_driver) { - ppc_driver->ConfigPrivilege(pos, PPC_SSE123_SECURE_CONFIG, - PPC_SSE123_PRIV_CONFIG); - } -} - -void ppc_configure_to_secure_unpriv(enum ppc_bank_e bank, uint32_t pos) -{ - DRIVER_PPC_SSE123 *ppc_driver; - - if (bank >= PPC_BANK_COUNT) { - return; - } - - ppc_driver = ppc_bank_drivers[bank]; - if (ppc_driver) { - ppc_driver->ConfigPrivilege(pos, PPC_SSE123_SECURE_CONFIG, - PPC_SSE123_PRIV_AND_NONPRIV_CONFIG); - } -} - -void ppc_clear_irq(void) -{ - Driver_PPC_SSE123_AHB_EXP0.ClearInterrupt(); - Driver_PPC_SSE123_APB.ClearInterrupt(); - Driver_PPC_SSE123_APB_EXP2.ClearInterrupt(); - Driver_PPC_SSE123_APB_EXP3.ClearInterrupt(); -} diff --git a/platform/ext/target/mps2/an539/target_cfg.h b/platform/ext/target/mps2/an539/target_cfg.h deleted file mode 100644 index 66a3a1247a..0000000000 --- a/platform/ext/target/mps2/an539/target_cfg.h +++ /dev/null @@ -1,172 +0,0 @@ -/* - * Copyright (c) 2019-2020 Arm Limited. All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __TARGET_CFG_H__ -#define __TARGET_CFG_H__ - -#include <stdint.h> - -#define TFM_DRIVER_STDIO Driver_USART0 -#define NS_DRIVER_STDIO Driver_USART0 - -enum ppc_bank_e { - PPC_SP_DO_NOT_CONFIGURE = -1, - PPC_SP_AHB_PPC_EXP0 = 0, - PPC_SP_APB_PPC = 1, - PPC_SP_APB_PPC_EXP0 = 2, - PPC_SP_APB_PPC_EXP1 = 3, - PPC_SP_APB_PPC_EXP2 = 4, - PPC_SP_APB_PPC_EXP3 = 5, -}; - -/** - * \brief MPU configs - */ -#define PRIVILEGED_DEFAULT_ENABLE 1 -#define HARDFAULT_NMI_ENABLE 1 - -/** - * \brief Store the addresses of memory regions - */ -struct memory_region_limits { - uint32_t non_secure_code_start; - uint32_t non_secure_partition_base; - uint32_t non_secure_partition_limit; - uint32_t veneer_base; - uint32_t veneer_limit; -#ifdef BL2 - uint32_t secondary_partition_base; - uint32_t secondary_partition_limit; -#endif /* BL2 */ -}; - -/** - * \brief Holds the data necessary to do isolation for a specific peripheral. - */ -struct platform_data_t { - uint32_t periph_start; - uint32_t periph_limit; - enum ppc_bank_e periph_ppc_bank; - int16_t periph_ppc_loc; -}; - -/** - * \brief Forward declaration - */ -struct mpu_armv8m_region_cfg_t; - -/** - * \brief Enables the fault handlers BusFault, UsageFault, - * MemManageFault and SecureFault. - */ -enum tfm_plat_err_t enable_fault_handlers(void); - -/** - * \brief Configures the system reset request properties - * - * \return Returns values as specified by the \ref tfm_plat_err_t - */ -enum tfm_plat_err_t system_reset_cfg(void); - -/** - * \brief Configures all external interrupts to target the - * NS state, apart for the ones associated to secure - * peripherals (plus MPC and PPC) - */ -enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void); - -/** - * \brief This function enable the interrupts associated - * to the secure peripherals (plus MPC and PPC) - */ -enum tfm_plat_err_t nvic_interrupt_enable(void); - -/** - * \brief This function enables the MPU - */ -enum mpu_armv8m_error_t mpu_enable(uint32_t privdef_en, uint32_t hfnmi_en); - -/** - * \brief This function disables the MPU - */ -enum mpu_armv8m_error_t mpu_disable(void); - -/** - * \brief This function enables the given MPU region - */ -enum mpu_armv8m_error_t mpu_region_enable( - struct mpu_armv8m_region_cfg_t *region_cfg); - -/** - * \brief This function dsables the given MPU region - */ -enum mpu_armv8m_error_t mpu_region_disable(uint32_t region_nr); - -/** - * \brief This function cleans all the MPU regions configs - */ -enum mpu_armv8m_error_t mpu_clean(void); - -/** - * \brief Configures the Memory Protection Controller. - */ -enum tfm_plat_err_t mpc_init_cfg(void); - -/** - * \brief Clear MPC interrupt. - */ -void mpc_clear_irq(void); - -/** - * \brief Configures the Peripheral Protection Controller. - */ -enum tfm_plat_err_t ppc_init_cfg(void); - -/** - * \brief Restict peripheral access to secure access only - * - * \note The function does not configure privilege - */ -void ppc_configure_to_secure(enum ppc_bank_e bank, uint32_t pos); - -/** - * \brief Allow non-secure access to peripheral - * - * \note The function does not configure privilege - */ -void ppc_configure_to_non_secure(enum ppc_bank_e bank, uint32_t pos); - -/** - * \brief Restict access to peripheral to privileged in secure state - */ -void ppc_configure_to_secure_priv(enum ppc_bank_e bank, uint32_t pos); - -/** - * \brief Enable unprivileged access to peripheral in secure state - */ -void ppc_configure_to_secure_unpriv(enum ppc_bank_e bank, uint32_t pos); - -/** - * \brief Clears PPC interrupt. - */ -void ppc_clear_irq(void); - -/** - * \brief Configures SAU and IDAU. - */ -void sau_and_idau_cfg(void); - -#endif /* __TARGET_CFG_H__ */ diff --git a/platform/ext/target/mps2/an539/tfm_peripherals_def.h b/platform/ext/target/mps2/an539/tfm_peripherals_def.h deleted file mode 100644 index eb270206f8..0000000000 --- a/platform/ext/target/mps2/an539/tfm_peripherals_def.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2019, Arm Limited. All rights reserved. - * Copyright (c) 2020, Cypress Semiconductor Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef __TFM_PERIPHERALS_DEF_H__ -#define __TFM_PERIPHERALS_DEF_H__ - -#include "platform_irq.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define TFM_TIMER0_IRQ (TIMER0_IRQn) -#define TFM_TIMER1_IRQ (TIMER1_IRQn) - -struct platform_data_t; - -extern struct platform_data_t tfm_peripheral_std_uart; -extern struct platform_data_t tfm_peripheral_fpga_io; -extern struct platform_data_t tfm_peripheral_timer0; - -#define TFM_PERIPHERAL_STD_UART (&tfm_peripheral_std_uart) -#define TFM_PERIPHERAL_FPGA_IO (&tfm_peripheral_fpga_io) -#define TFM_PERIPHERAL_TIMER0 (&tfm_peripheral_timer0) - -#ifdef __cplusplus -} -#endif - -#endif /* __TFM_PERIPHERALS_DEF_H__ */ |