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-rw-r--r--platform/ext/target/lairdconnectivity/common/bl5340/target_cfg.c5
-rw-r--r--platform/ext/target/nordic_nrf/common/nrf5340/target_cfg.c5
-rw-r--r--platform/ext/target/nordic_nrf/common/nrf9160/target_cfg.c6
3 files changed, 16 insertions, 0 deletions
diff --git a/platform/ext/target/lairdconnectivity/common/bl5340/target_cfg.c b/platform/ext/target/lairdconnectivity/common/bl5340/target_cfg.c
index a5734e757b..8077176af1 100644
--- a/platform/ext/target/lairdconnectivity/common/bl5340/target_cfg.c
+++ b/platform/ext/target/lairdconnectivity/common/bl5340/target_cfg.c
@@ -282,6 +282,11 @@ enum tfm_plat_err_t spu_periph_init_cfg(void)
nrf_gpio_pin_mcu_select(PIN_XL1, NRF_GPIO_PIN_MCUSEL_PERIPHERAL);
nrf_gpio_pin_mcu_select(PIN_XL2, NRF_GPIO_PIN_MCUSEL_PERIPHERAL);
+ /* Enable the instruction and data cache (this can be done only from secure
+ * code; that's why it is placed here).
+ */
+ NRF_CACHE->ENABLE = CACHE_ENABLE_ENABLE_Enabled;
+
return TFM_PLAT_ERR_SUCCESS;
}
diff --git a/platform/ext/target/nordic_nrf/common/nrf5340/target_cfg.c b/platform/ext/target/nordic_nrf/common/nrf5340/target_cfg.c
index 8239fd5f4a..69bbcaedc6 100644
--- a/platform/ext/target/nordic_nrf/common/nrf5340/target_cfg.c
+++ b/platform/ext/target/nordic_nrf/common/nrf5340/target_cfg.c
@@ -274,6 +274,11 @@ enum tfm_plat_err_t spu_periph_init_cfg(void)
nrf_gpio_pin_mcu_select(PIN_XL1, NRF_GPIO_PIN_MCUSEL_PERIPHERAL);
nrf_gpio_pin_mcu_select(PIN_XL2, NRF_GPIO_PIN_MCUSEL_PERIPHERAL);
+ /* Enable the instruction and data cache (this can be done only from secure
+ * code; that's why it is placed here).
+ */
+ NRF_CACHE->ENABLE = CACHE_ENABLE_ENABLE_Enabled;
+
return TFM_PLAT_ERR_SUCCESS;
}
diff --git a/platform/ext/target/nordic_nrf/common/nrf9160/target_cfg.c b/platform/ext/target/nordic_nrf/common/nrf9160/target_cfg.c
index 277e1829bc..17d786170f 100644
--- a/platform/ext/target/nordic_nrf/common/nrf9160/target_cfg.c
+++ b/platform/ext/target/nordic_nrf/common/nrf9160/target_cfg.c
@@ -22,6 +22,7 @@
#include <spu.h>
#include <nrfx.h>
+#include <hal/nrf_nvmc.h>
struct platform_data_t tfm_peripheral_timer0 = {
NRF_TIMER0_S_BASE,
@@ -230,6 +231,11 @@ enum tfm_plat_err_t spu_periph_init_cfg(void)
/* GPIO pin configuration */
spu_gpio_config_non_secure(0, false);
+ /* Enable the instruction cache (this can be done only from secure code;
+ * that's why it is placed here).
+ */
+ nrf_nvmc_icache_config_set(NRF_NVMC, NRF_NVMC_ICACHE_ENABLE);
+
return TFM_PLAT_ERR_SUCCESS;
}