aboutsummaryrefslogtreecommitdiff
path: root/platform/ext/target/arm/mps2/an521/cmsis_core/cmsis_cpu.h
diff options
context:
space:
mode:
Diffstat (limited to 'platform/ext/target/arm/mps2/an521/cmsis_core/cmsis_cpu.h')
-rw-r--r--platform/ext/target/arm/mps2/an521/cmsis_core/cmsis_cpu.h32
1 files changed, 32 insertions, 0 deletions
diff --git a/platform/ext/target/arm/mps2/an521/cmsis_core/cmsis_cpu.h b/platform/ext/target/arm/mps2/an521/cmsis_core/cmsis_cpu.h
new file mode 100644
index 0000000000..f3ee2ae6a6
--- /dev/null
+++ b/platform/ext/target/arm/mps2/an521/cmsis_core/cmsis_cpu.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2016-2022 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_CPU_H__
+#define __CMSIS_CPU_H__
+
+/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */
+#define __CM33_REV 0x0000U /* Core revision r0p1 */
+#define __MPU_PRESENT 1U /* MPU present */
+#define __SAUREGION_PRESENT 1U /* SAU regions present */
+#define __VTOR_PRESENT 1U /* VTOR present */
+#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /* FPU present */
+#define __DSP_PRESENT 0U /* no DSP extension present */
+
+#include "core_cm33.h"
+
+#endif /* __CMSIS_CPU_H__ */