diff options
Diffstat (limited to 'platform/ext/common/iar/tfm_common_s.icf')
-rw-r--r-- | platform/ext/common/iar/tfm_common_s.icf | 302 |
1 files changed, 181 insertions, 121 deletions
diff --git a/platform/ext/common/iar/tfm_common_s.icf b/platform/ext/common/iar/tfm_common_s.icf index c9d49e9c05..fb456e17d5 100644 --- a/platform/ext/common/iar/tfm_common_s.icf +++ b/platform/ext/common/iar/tfm_common_s.icf @@ -1,6 +1,8 @@ /* - * Copyright (c) 2017-2021 Arm Limited. All rights reserved. + * Copyright (c) 2017-2023 Arm Limited. All rights reserved. * Copyright (c) 2020-2021 IAR Systems AB + * Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) + * or an affiliate of Cypress Semiconductor Corporation. All rights reserved. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -19,51 +21,82 @@ #include "region_defs.h" -define block ER_TFM_CODE with fixed order, alignment = 8, maximum size = S_CODE_SIZE { - readonly section .intvec, -#ifndef S_RAM_CODE_START - rw section .textrw object *.o, /* place __ramfunc in ROM if no TFM_RAM_CODE block */ +/* Include file with definitions for section alignments. + * Note: it should be included after region_defs.h to let platform define + * default values if needed. */ +#include "tfm_s_linker_alignments.h" + +define block ER_VECTORS with size = S_CODE_VECTOR_TABLE_SIZE { + readonly section .intvec +}; + +#ifdef CONFIG_TFM_USE_TRUSTZONE + /* + * Place the CMSE Veneers (containing the SG instruction) in a separate + * at least 32 bytes aligned region so that the SAU can be programmed to + * just set this region as Non-Secure Callable. + */ +define block ER_VENEER with alignment = TFM_LINKER_VENEERS_ALIGNMENT {section Veneer$$CMSE}; + +define block VENEER_ALIGN with alignment = TFM_LINKER_VENEERS_ALIGNMENT, size = 0 { }; #endif - readonly + +define block ER_TFM_CODE with fixed order, alignment = 8, maximum size = S_CODE_SIZE { + ro section .text object *startup*, + ro section .text object *libplatform_s*, + ro section .rodata object *libplatform_s*, + ro object *libtfm_spm*, }; -define block TFM_UNPRIV_CODE with alignment = 32 { - section SFN, - ro section .rodata object tfm_*_secure_api.o, - ro object *6M_tl*.a, - ro object *7M_tl*.a, - ro object *libtfm_sprt.a, - ro object psa_client.o, - ro object psa_service.o, - ro object psa_lifecycle.o, - ro object tfm_log_raw.o +define block TFM_UNPRIV_CODE_START with alignment = TFM_LINKER_UNPRIV_CODE_ALIGNMENT { + readonly }; + /* + * This empty, zero long execution region is here to mark the end address + * of TFM unprivileged code. + */ +define block TFM_UNPRIV_CODE_END with alignment = TFM_LINKER_UNPRIV_CODE_ALIGNMENT, size = 0 { }; + + /**** Section for holding partition RO load data */ + /* + * Sort the partition info by priority to guarantee the initing order. + * The first loaded partition will be inited at last in SFN model. + */ +define block TFM_SP_LOAD_LIST with alignment = 4 { + ro section .part_load_priority_00 object load_info_*.o, + ro section .part_load_priority_01 object load_info_*.o, + ro section .part_load_priority_02 object load_info_*.o, + ro section .part_load_priority_03 object load_info_*.o, +}; + /**** PSA RoT RO part (CODE + RODATA) start here */ /* * This empty, zero long execution region is here to mark the start address * of PSA RoT code. */ -define block TFM_PSA_CODE_START with alignment = 32, size = 0 { }; +define block TFM_PSA_CODE_START with alignment = TFM_LINKER_PSA_ROT_LINKER_CODE_ALIGNMENT, size = 0 { }; - define block TFM_PSA_ROT_LINKER with alignment = 32 { - ro object *tfm_psa_rot_partition*, +define block TFM_PSA_ROT_LINKER with alignment = TFM_LINKER_PSA_ROT_LINKER_CODE_ALIGNMENT { + ro object *tfm_psa_rot_partition*, + section TFM_*_PSA-ROT_ATTR_FN object *libplatform_s*, + section TFM_*_PSA-ROT_ATTR_FN object *.o, }; /* * This empty, zero long execution region is here to mark the end address * of PSA RoT code. */ -define block TFM_PSA_CODE_END with alignment = 32, size = 0 { }; +define block TFM_PSA_CODE_END with alignment = TFM_LINKER_PSA_ROT_LINKER_CODE_ALIGNMENT, size = 0 { }; /**** APPLICATION RoT RO part (CODE + RODATA) start here */ /* * This empty, zero long execution region is here to mark the start address * of APP RoT code. */ -define block TFM_APP_CODE_START with alignment = 32, size = 0 { }; +define block TFM_APP_CODE_START with alignment = TFM_LINKER_APP_ROT_LINKER_CODE_ALIGNMENT, size = 0 { }; - define block TFM_APP_ROT_LINKER with alignment = 32 { + define block TFM_APP_ROT_LINKER with alignment = TFM_LINKER_APP_ROT_LINKER_CODE_ALIGNMENT { ro object *tfm_app_rot_partition*, }; @@ -71,53 +104,60 @@ define block TFM_APP_CODE_START with alignment = 32, size = 0 { }; * This empty, zero long execution region is here to mark the end address * of APP RoT code. */ -define block TFM_APP_CODE_END with alignment = 32, size = 0 { }; - -#if defined(S_CODE_SRAM_ALIAS_BASE) - /* eFlash driver code that gets copied from Flash to SRAM */ -define block ER_CODE_SRAM with alignment = 4 { - ro object Driver_GFC100_EFlash.o, - ro object gfc100_eflash_drv.o, - ro object musca_b1_eflash_drv.o +define block TFM_APP_CODE_END with alignment = TFM_LINKER_APP_ROT_LINKER_CODE_ALIGNMENT, size = 0 { }; + +#if defined(S_RAM_CODE_START) + /* Flash drivers code that gets copied from Flash */ + initialize by copy { + ro object *libflash_drivers*, }; -place at address S_CODE_SRAM_ALIAS_BASE { block ER_CODE_SRAM }; + + define block ER_CODE_SRAM with fixed order, alignment = 4, maximum size = S_RAM_CODE_SIZE { + rw section .text, + rw section .rodata, + rw section .textrw, /* __ramfunc */ + }; + +place at address S_RAM_CODE_START { block ER_CODE_SRAM }; #endif /**** Base address of secure data area */ define block TFM_SECURE_DATA_START with size = 0 { }; -#ifndef TFM_MULTI_CORE_TOPOLOGY +#if ((defined(__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) || \ + (defined(__ARM8M_BASELINE__) && (__CORE__ == __ARM8M_BASELINE__)) || \ + (defined(__ARM8EM_MAINLINE__) && (__CORE__ == __ARM8EM_MAINLINE__))) /* Shared area between BL2 and runtime to exchange data */ -define block TFM_SHARED_DATA with alignment = 32, size = BOOT_TFM_SHARED_DATA_SIZE { }; -define block ARM_LIB_STACK_MSP with alignment = 32, size = S_MSP_STACK_SIZE { }; +define block TFM_SHARED_DATA with alignment = TFM_LINKER_BL2_SHARED_DATA_ALIGNMENT, size = BOOT_TFM_SHARED_DATA_SIZE { }; +define block ARM_LIB_STACK with alignment = TFM_LINKER_MSP_STACK_ALIGNMENT, size = S_MSP_STACK_SIZE - 0x8 { }; define overlay STACK_DATA {block TFM_SHARED_DATA}; -define overlay STACK_DATA {block ARM_LIB_STACK_MSP}; - -# if !defined(TFM_PSA_API) - /* Reserve space for stack seal (8 bytes) */ -define block ARM_LIB_STACK with alignment = 32, size = S_PSP_STACK_SIZE - 0x8 { }; -define block ARM_LIB_STACK_SEAL with size = 0x8 { }; -# else -define block ARM_LIB_STACK with alignment = 32, size = S_PSP_STACK_SIZE { }; -# endif -keep {block TFM_SHARED_DATA, block ARM_LIB_STACK_MSP}; -#endif +define overlay STACK_DATA {block ARM_LIB_STACK}; -#if !defined(TFM_PSA_API) -define block TFM_SECURE_STACK with size = 0x2000, alignment = 128 {}; -keep {block TFM_SECURE_STACK}; -#endif /* !defined(TFM_PSA_API) */ +define block STACKSEAL with size = 0x8 { }; -#if defined(TFM_SP_META_PTR_ENABLE) -define block TFM_SP_META_PTR_ENABLE with alignment = 32 { - section SP_META_PTR_SPRTL_INST +keep {block TFM_SHARED_DATA, block ARM_LIB_STACK}; +#endif /* (defined(__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) || \ + * (defined(__ARM8M_BASELINE__) && (__CORE__ == __ARM8M_BASELINE__)) || \ + * (defined(__ARM8EM_MAINLINE__) && (__CORE__ == __ARM8EM_MAINLINE__)) */ + +#if defined(CONFIG_TFM_PARTITION_META) +define block TFM_SP_META_PTR with alignment = TFM_LINKER_SP_META_PTR_ALIGNMENT { + zi section .bss.SP_META_PTR_SPRTL_INST }; + + /* + * This empty, zero long execution region is here to mark the end address + * of TFM partition metadata pointer region. + */ +define block TFM_SP_META_PTR_END with alignment = TFM_LINKER_SP_META_PTR_ALIGNMENT, size = 0 { }; #endif -define block TFM_APP_RW_STACK_START with alignment = 32, size = 0 { }; +define block TFM_APP_RW_STACK_START with alignment = TFM_LINKER_APP_ROT_LINKER_DATA_ALIGNMENT, size = 0 { }; - define block TFM_APP_ROT_LINKER_DATA with alignment = 32 { - rw object *tfm_app_rot_partition*, +define block TFM_APP_ROT_LINKER_DATA with alignment = TFM_LINKER_APP_ROT_LINKER_DATA_ALIGNMENT { + rw object *tfm_app_rot_partition*, + section TFM_*_APP-ROT_ATTR_RW object *.o, + section TFM_*_APP-ROT_ATTR_ZI object *.o, }; @@ -125,67 +165,82 @@ define block TFM_APP_RW_STACK_START with alignment = 32, size = 0 { }; * This empty, zero long execution region is here to mark the end address * of APP RoT RW and Stack. */ -define block TFM_APP_RW_STACK_END with alignment = 32, size = 0 { }; +define block TFM_APP_RW_STACK_END with alignment = TFM_LINKER_APP_ROT_LINKER_DATA_ALIGNMENT, size = 0 { }; -#if TFM_MULTI_CORE_TOPOLOGY && defined(S_DATA_PRIV_START) - /**** Privileged data area base address specified by multi-core platform */ +#if ((defined(__ARM6M__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARM7M__) && (__CORE__ == __ARM7M__)) || \ + (defined(__ARM7EM__) && (__CORE__ == __ARM7EM__))) +#ifdef S_DATA_PRIV_START + /**** Privileged data area base address specified by Armv6-M/v7-M platform */ define block TFM_SECURE_PRIV_DATA_BOUNDARY with size = 0 { }; #endif -#if TFM_MULTI_CORE_TOPOLOGY /* * Move BL2 shared area and MSP stack to the beginning of privileged data - * area in multi-core topology. + * area on Armv6-M/v7-M platforms. */ /* Shared area between BL2 and runtime to exchange data */ -define block TFM_SHARED_DATA with alignment = 32, size = BOOT_TFM_SHARED_DATA_SIZE { }; +define block TFM_SHARED_DATA with alignment = TFM_LINKER_BL2_SHARED_DATA_ALIGNMENT, size = BOOT_TFM_SHARED_DATA_SIZE { }; /* MSP */ -define block ARM_LIB_STACK_MSP with alignment = 32, size = S_MSP_STACK_SIZE { }; +define block ARM_LIB_STACK with alignment = TFM_LINKER_MSP_STACK_ALIGNMENT, size = S_MSP_STACK_SIZE { }; define overlay STACK_DATA {block TFM_SHARED_DATA}; -define overlay STACK_DATA {block ARM_LIB_STACK_MSP}; +define overlay STACK_DATA {block ARM_LIB_STACK}; - /* PSP is privileged in multi-core topology */ -define block ARM_LIB_STACK with alignment = 32, size = S_PSP_STACK_SIZE { }; -keep {block TFM_SHARED_DATA, block ARM_LIB_STACK_MSP}; -#endif +keep {block TFM_SHARED_DATA, block ARM_LIB_STACK}; +#endif /* (defined(__ARM6M__) && (__CORE__ == __ARM6M__)) || \ + * (defined(__ARM7M__) && (__CORE__ == __ARM7M__)) || \ + * (defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)) */ -define block HEAP with alignment = 8, size = S_HEAP_SIZE { }; -define block ARM_LIB_HEAP with alignment = 8, size = S_HEAP_SIZE { }; -define overlay HEAP_OVL {block HEAP}; -define overlay HEAP_OVL {block ARM_LIB_HEAP}; -keep {block HEAP, block ARM_LIB_HEAP}; +#if defined(ENABLE_HEAP) + define block HEAP with alignment = 8, size = S_HEAP_SIZE { }; + define block ARM_LIB_HEAP {block HEAP}; + keep {block HEAP, block ARM_LIB_HEAP}; +#endif define block ER_TFM_DATA with alignment = 8 {readwrite}; +/* The runtime partition placed order is same as load partition */ +define block ER_PART_RT_POOL with alignment = 4 { + zi section .bss.part_runtime_priority_00, + zi section .bss.part_runtime_priority_01, + zi section .bss.part_runtime_priority_02, + zi section .bss.part_runtime_priority_03, +}; + +/* The runtime service placed order is same as load partition */ +define block ER_SERV_RT_POOL with alignment = 4 { + zi section .bss.serv_runtime_priority_00, + zi section .bss.serv_runtime_priority_01, + zi section .bss.serv_runtime_priority_02, + zi section .bss.serv_runtime_priority_03, +}; + +keep {block ER_PART_RT_POOL, block ER_SERV_RT_POOL}; + /**** PSA RoT DATA start here */ /* * This empty, zero long execution region is here to mark the start address * of PSA RoT RW and Stack. */ -define block TFM_PSA_RW_STACK_START with alignment = 32, size = 0 { }; +define block TFM_PSA_RW_STACK_START with alignment = TFM_LINKER_PSA_ROT_LINKER_DATA_ALIGNMENT, size = 0 { }; - define block TFM_PSA_ROT_LINKER_DATA with alignment = 32 { - rw object *tfm_psa_rot_partition*, - }; +define block TFM_PSA_ROT_LINKER_DATA with alignment = TFM_LINKER_PSA_ROT_LINKER_DATA_ALIGNMENT { + rw object *tfm_psa_rot_partition*, + section TFM_*_PSA-ROT_ATTR_RW object *.o, + section TFM_*_PSA-ROT_ATTR_ZI object *.o, +}; /* * This empty, zero long execution region is here to mark the end address * of PSA RoT RW and Stack. */ -define block TFM_PSA_RW_STACK_END with alignment = 32, size = 0x0 { }; +define block TFM_PSA_RW_STACK_END with alignment = TFM_LINKER_PSA_ROT_LINKER_DATA_ALIGNMENT, size = 0x0 { }; #ifdef RAM_VECTORS_SUPPORT -define block ER_RAM_VECTORS with alignment = 256 { section .ramvec }; -#endif - -#if defined (S_RAM_CODE_START) -define block TFM_RAM_CODE with alignment = 8 { - rw section .textrw, /* __ramfunc */ -}; -place at address S_RAM_CODE_START { block TFM_RAM_CODE }; +define block ER_RAM_VECTORS with alignment = TFM_LINKER_RAM_VECTORS_ALIGNMENT { section .ramvec }; #endif /* This empty, zero long execution region is here to mark the limit address @@ -193,9 +248,18 @@ place at address S_RAM_CODE_START { block TFM_RAM_CODE }; */ define block SRAM_WATERMARK with size = 0 { }; -define block LR_CODE with fixed order { +define block LR_CODE with fixed order, maximum size = S_CODE_SIZE { + block ER_VECTORS, +#ifdef CONFIG_TFM_USE_TRUSTZONE + block ER_VENEER, + block VENEER_ALIGN, +#endif block ER_TFM_CODE, - block TFM_UNPRIV_CODE, + block TFM_UNPRIV_CODE_START, + block TFM_UNPRIV_CODE_END, + + block TFM_SP_LOAD_LIST, + block TFM_PSA_CODE_START, block TFM_PSA_ROT_LINKER, @@ -243,30 +307,26 @@ define block DATA with fixed order { * MPU on Armv6-M/v7-M core in multi-core topology may require more strict * alignment that MPU region base address must align with the MPU region * size. - * As a result, in multi-core topology, to save memory resource and MPU + * As a result, on Armv6-M/v7-M cores, to save memory resource and MPU * regions, unprivileged data sections and privileged data sections are * separated and gathered in unprivileged/privileged data area respectively. * Keep BL2 shared data and MSP stack at the beginning of the secure data - * area in single Armv8-M topology, while move the two areas to the - * beginning of privileged data region in multi-core topology. + * area on Armv8-M cores, while move the two areas to the beginning of + * privileged data region on Armv6-M/v7-M cores. */ -#ifndef TFM_MULTI_CORE_TOPOLOGY +#if ((defined(__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) || \ + (defined(__ARM8M_BASELINE__) && (__CORE__ == __ARM8M_BASELINE__)) || \ + (defined(__ARM8EM_MAINLINE__) && (__CORE__ == __ARM8EM_MAINLINE__))) /* Shared area between BL2 and runtime to exchange data */ overlay STACK_DATA, - /* PSP is unprivileged in single-core topology */ - block ARM_LIB_STACK, -# if !defined(TFM_PSA_API) - /* Define stack seal block for Library mode */ - block ARM_LIB_STACK_SEAL, -# endif -#endif + block STACKSEAL, +#endif /* (defined(__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) || \ + * (defined(__ARM8M_BASELINE__) && (__CORE__ == __ARM8M_BASELINE__)) || \ + * (defined(__ARM8EM_MAINLINE__) && (__CORE__ == __ARM8EM_MAINLINE__)) */ -#if !defined(TFM_PSA_API) - block TFM_SECURE_STACK, -#endif /* !defined(TFM_PSA_API) */ - -#if defined(TFM_SP_META_PTR_ENABLE) +#if defined(CONFIG_TFM_PARTITION_META) block TFM_SP_META_PTR, + block TFM_SP_META_PTR_END, #endif /**** APP RoT DATA start here */ @@ -284,9 +344,11 @@ define block DATA with fixed order { */ block TFM_APP_RW_STACK_END, -#ifdef TFM_MULTI_CORE_TOPOLOGY +#if ((defined(__ARM6M__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARM7M__) && (__CORE__ == __ARM7M__)) || \ + (defined(__ARM7EM__) && (__CORE__ == __ARM7EM__))) #ifdef S_DATA_PRIV_START - /**** Privileged data area base address specified by multi-core platform */ + /**** Privileged data area base address specified by Armv6-M/v7-M platform */ }; define block PRIV_DATA with fixed order { block TFM_SECURE_PRIV_DATA_BOUNDARY, @@ -294,18 +356,24 @@ define block PRIV_DATA with fixed order { /* * Move BL2 shared area and MSP stack to the beginning of privileged data - * area in multi-core topology. + * area on Armv6-M/v7-M platforms. */ /* Shared area between BL2 and runtime to exchange data */ overlay STACK_DATA, - /* PSP is privileged in multi-core topology */ - block ARM_LIB_STACK, -#endif +#endif /* (defined(__ARM6M__) && (__CORE__ == __ARM6M__)) || \ + * (defined(__ARM7M__) && (__CORE__ == __ARM7M__)) || \ + * (defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)) */ - overlay HEAP_OVL, +#if defined(ENABLE_HEAP) + block ARM_LIB_HEAP, +#endif block ER_TFM_DATA, + block ER_PART_RT_POOL, + + block ER_SERV_RT_POOL, + /**** PSA RoT DATA start here */ /* * This empty, zero long execution region is here to mark the start address @@ -335,20 +403,12 @@ define block PRIV_DATA with fixed order { }; place at address S_DATA_START { block DATA }; -#if defined(TFM_MULTI_CORE_TOPOLOGY) && defined(S_DATA_PRIV_START) +#if ((defined(__ARM6M__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARM7M__) && (__CORE__ == __ARM7M__)) || \ + (defined(__ARM7EM__) && (__CORE__ == __ARM7EM__))) && defined(S_DATA_PRIV_START) place at address S_DATA_PRIV_START { block PRIV_DATA }; #endif -#ifndef TFM_MULTI_CORE_TOPOLOGY - /* - * Place the CMSE Veneers (containing the SG instruction) in a separate - * 32 bytes aligned region so that the SAU can be programmed to - * just set this region as Non-Secure Callable. - */ -define block LR_VENEER with alignment = 0x20, size = CMSE_VENEER_REGION_SIZE {section Veneer$$CMSE}; -place at address CMSE_VENEER_REGION_START {block LR_VENEER}; -#endif - /* Reserved place for NS application. * No code will be placed here, just address of this region is used in the * secure code to configure certain HW components. This generates an empty |